Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
1. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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3. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9-17 of U.S. Patent No. 12,242,856. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application would be anticipated by those of ‘856.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-4 and 6-20 are rejected under 35 U.S.C. 103 as being unpatentable over Joao et al (US 2018/0276046, cited in the IDS dated February 6th, 2025, herein Joao) in view of Valerio et al (US 2020/0218539, herein Valerio).
Regarding claim 1, Joao teaches a method of operating a data processor in which execution threads may execute program instructions to perform processing operations, the data processor comprising:
an execution unit operable to execute instructions in a program to be executed to perform processing operations for execution threads executing the program ([0046], execute stage 14); and
a cache operable to store data values for use when executing instructions to perform processing operations for execution threads ([0046], instruction cache 6, data cache 20);
the method comprising: when the execution unit is executing a program comprising a set of one or more instructions for a plurality of execution threads ([0047], threaded execution):
monitoring the operation of the cache during execution of the program for the plurality of execution threads ([0038-0039], [0047], cache monitoring by performance monitor circuitry); and
determining, using a threshold for at least one performance metric for the cache, whether the cache is in a particular cache operating state ([0034], [0040], claim 15, counter to indicate threshold of hardware resource availability or contention); and
when it is determined that the cache is in the particular cache operating state, controlling an operation of the data processor so that a number of instructions for execution threads of the plurality of execution threads issued to the execution unit for executing the program is reduced ([0049], controlling thread activity based on monitoring data, [0060], mitigate thrashing by reducing number of active threads);
wherein the threshold for the at least one performance metric for the cache that is used to determine whether the cache has entered the particular operating state is based on a measure of how much data the program will be passing through the cache ([0034], [0040], claim 15, counter to indicate threshold of hardware resource availability or contention & [0050], thread scheduling circuitry to control amount of active threads based on performance monitoring).
Joao fails to explicitly teach wherein the operating state is a high pressure cache operating state, or wherein the threshold is varied in use.
Valerio teaches a method of operating a data processor comprising determining, using a threshold for at least one performance metric for the cache, whether the cache is in a particular high pressure cache operating state ([0165], [0183], threshold of cache stress metric), wherein the threshold is varied in use ([0165-0166], configurable threshold).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Joao and Valerio to utilize the performance metric threshold as a variable means of detecting a high pressure state in the cache. While Joao does not explicitly state that the cache operating state is indicative of a “high pressure” state, both Joao and Valerio disclose the use of a monitored state of a cache being used to control the dispatch of threads in the processor. As both Joao and Valerio disclose multithreaded execution paradigms, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Joao and Valerio teaches the method of claim 1, wherein the cache is a load/store cache, a texture cache, or a translation lookaside buffer (Joao [0049], data cache & TLB).
Regarding claim 3, the combination of Joao and Valerio teaches the method of claim 1, comprising monitoring the operation of the cache during execution of the program for the plurality of execution threads by tracking one or more performance metrics that are indicative of the utilisation of the cache (Joao [0049], monitoring of cache usage by PMC 40).
Regarding claim 4, the combination of Joao and Valerio teaches the method of claim 3, comprising tracking one or more of the following performance metrics for the cache: a measure of the cache tag re-allocation rate; a measure of the number of cache lines being filled; and a measure of the miss rate for the cache (Joao [0038-0039], conflict and allocation metrics tracking).
Regarding claim 6, the combination of Joao and Valerio teaches the method of claim 1, comprising stalling the issuing of new threads when the cache operation monitoring indicates that the cache is in a particular cache operating state (Joao [0060], mitigate thrashing by reducing number of active threads).
Regarding claim 7, the combination of Joao and Valerio teaches the method of claim 1, wherein there is a minimum thread count below which the issuing of execution threads is not reduced (Joao [0040], [0063], thread restoration event occurs when number of active threads is below number of software-scheduled threads).
Regarding claim 8, the combination of Joao and Valerio teaches the method of claim 1, wherein the data processor comprises plural different types of caches (Joao [0046], multi-level instruction and data caches), and the method comprises controlling the operation of the data processor based on which of the plural caches execution threads will use when executing a program (Joao [0038-0039], [0049], monitoring different types of caches to control operation).
Regarding claim 9, the combination of Joao and Valerio teaches the method of claim 1, wherein the data processor is a graphics processor, and wherein the program is one of: a geometry shader program, a tessellation shader, a vertex shader program, a fragment shader program, or a compute shader program (Valerio [0054], multiple shader programs of graphics cores).
Regarding claim 10, the combination of Joao and Valerio teaches the method of claim 1, wherein the measure of how much data the program will be passing through the cache is based on a number of instructions in the program that will use the cache (Valerio [0161], [0165-0166], controlling processor based on a number of instructions in a kernel that will use a cache).
Regarding claim 11, the combination of Joao and Valerio teaches the method of claim 1, wherein the measure of how much data the program will be passing through the cache is determined at run time (Joao [0049-0050], scheduling based on runtime performance monitoring).
Claims 12-15 and 16-19 refer to a processor embodiment of the method embodiment of claims 1-4 and 6-9, respectively. Therefore, the above rejections for claims 1-4 and 6-9 are applicable to claims 12-15 and 16-19, respectively.
Claim 20 refers to a medium embodiment of the method embodiment of claim 1. The above rejection for claim 1 is therefore applicable to claim 10.
Allowable Subject Matter
5. Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, as well as resolving the double patenting rejection.
Claim 5 includes limitations regarding the use of a running average value which is weighted according to the size of an executing program of the processor which distinguishes the claim from the prior art when all of the limitations included within claim 5 and its parent claims are considered.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Krishnan (US 2019/0303303) discloses a processor that controls the issuing of instructions according to a threshold used to monitor a cache.
Feero (US 10,007,616) discloses a processor that controls a prefetch rate of a scheduling unit based on an availability of a cache reaching a threshold value.
Wang (US 2016/0092363) discloses a processor that monitors cache activity and scheduling threads to cores according to performance metrics of the cache.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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