Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-21 of U.S. Patent No. 12236992.
Current Application # 19039241
US Pat # 12236992
For example:
Claim 1:
1. A device comprising: a memory array having data cells and pattern cells; and a controller configured to: apply at least one voltage to the pattern cells to determine at least one characteristic of the data cells; and apply, based on the determined characteristic, at least one voltage to the data cells.
For example:
Claim 1:
A system comprising: a memory array comprising pattern cells and data cells, wherein each of the pattern cells is configured to store only a first logic state; sensing circuitry configured to read the pattern cells; and a controller configured to: store a codeword in the data cells; apply first voltages to the pattern cells; determine, using the sensing circuitry, that at least a portion of the pattern cells switch; determine, based on the portion of the pattern cells that switch, to refresh the codeword; and apply the refresh of the codeword.
14. The system of claim 1, wherein: applying the first voltages to the pattern cells comprises applying different respective voltages to each of multiple groups of the pattern cells; and the respective voltage for each group is higher than a read voltage applied to the data cells.
Even though the claims at issue are not identical but overall scope of the claims are identical and they are not patentably distinct from each other. For example, the above limitation “apply, based on the determined characteristic, at least one voltage to the data cells.” in current application 19039241 and the limitation “applying different respective voltages to each of multiple groups of the pattern cells; and the respective voltage for each group is higher than a read voltage applied to the data cells” in US Pat # 122236992 are not identical but overall scope of the claims are identical and they are not patentably distinct from each other.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Goda et al. (US Pub # 2009/0109743).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Goda et al. teach a device comprising: a memory array having data cells and pattern cells (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0097, 0104-0109, reference cells are pattern cell); and a controller configured to: apply at least one voltage to the pattern cells to determine at least one characteristic of the data cells; and apply, based on the determined characteristic, at least one voltage to the data cells (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0097, 0104-0109, Unit 1070 is controller, step 910-960).
Even though Goda et al. teach determining read reference voltage for the data cells based on reference cells but silent exclusively about determine at least one characteristic of the data cells. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Goda et al. where determining effective read reference voltage for the data cells would be called at least one characteristics of data cells in order to have effective read operation and to improve data retention for the data cells (see paragraph 0008).
Regarding claim 2, Goda et al. further teach, wherein each of the pattern cells is configured to store only a first logic state (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0097).
Regarding claim 3, Goda et al. further teach, wherein the voltage applied to the pattern cells is higher than the voltage applied to the data cells (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0097, 0104-0105).
Regarding claim 4, Goda et al. further teach, wherein applying the voltage to the pattern cells comprises applying ramps to the pattern cells (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0090).
Regarding claim 5, Goda et al. further teach, wherein applying the voltage to the pattern cells comprises applying steps to the pattern cells (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0091).
Regarding claim 6, Goda et al. further teach, wherein the memory array has a vertical array architecture comprising vertical bitlines or digit lines intersecting a plurality of horizontal decks of wordlines (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0096).
Regarding claim 7, Goda et al. further teach, wherein each deck is configured as two interdigitated wordline combs so that each bitline or digit line forms two cells at each of the decks (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0097, 0104-0106).
Regarding independent claim 8, Goda et al. teach a device comprising: a memory array having data cells and pattern cells (see Fig. 1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0097, 0104-0109, reference cells are pattern cell); and a controller configured to: apply a voltage to the pattern cells; and apply a voltage to the data cells, wherein the voltage applied to the pattern cells is higher than the voltage applied to the data cells (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0097, 0104-0109, Unit 1070 is controller, step 910-960).
Even though Goda et al. teach voltage applied for the data cells andn reference cells but silent exclusively about wherein the voltage applied to the pattern cells is higher than the voltage applied to the data cells. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Goda et al. where voltage applied to data cells about 15V-16V and voltage applied to pattern / reference cells 19V-20V (see specially paragraph 0043) i.e. pattern cells voltage is higher than data cells voltage in order to have effective program-read operation and to improve data retention for the data cells (see paragraph 0008).
Regarding claim 9, Goda et al. further teach, wherein the voltage applied to the data cells is a read voltage (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080).
Regarding claim 10, Goda et al. further teach, wherein the voltage is applied in multiple steps (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0089).
Regarding claim 11, Goda et al. further teach, wherein the pattern cells are arranged in multiple groups,and applying the voltage to the pattern cells comprises applying a voltage to a single group of the pattern cells (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0070).
Regarding claim 12, Goda et al. further teach, wherein the voltage applied to the single group is higher than a read voltage applied to the data cells (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0078).
Regarding claim 13, Goda et al. further teach, wherein applying the voltage to the pattern cells comprises applying different respective voltages to each of multiple groups of the pattern cells (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087).
Regarding claim 14, Goda et al. further teach, wherein the respective voltage for each group is higher than the voltage applied to the data cells (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0079).
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Goda et al. (US Pub # 2009/0109743) in view of Tran et al. (US Pub # 2023/0386543).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 15, Goda et al. teach a system comprising: a first group of memory cells; a second group of memory cells (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0097, 0104-0109, first group data cells, second group reference cells); and a controller configured to determine, based on whether the first group or the second group has switched, to refresh a codeword (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0097, 0104-0109, Unit 1070 is controller, step 910-960, write-read operation confirmed switching for cells).
Goda et al. is silent about refresh a code word.
Tran et al. teach refresh a code word (see paragraph 0005-0006, 0059-0060, 0145, 0167).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Tran et al. to the teaching of Goda et al. where refreshing codeword as taught by Tran et al. would be implemented for reference cells of Goda et al. in order to improve endurance of memory cells (see Tran et al, paragraph 0050).
Further reason to combine the teachings of Tran et al. and Goda et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards memory array including data cells and pattern cells.
Regarding claim 16, Goda et al. further teach wherein each of the memory cells in the first and second groups is configured to store only a first logic state (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0097).
Regarding claim 17, Goda et al. further teach, wherein the controller is further configured to store the codeword in data cells, and apply the refresh of the codeword (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0091).
Regarding claim 18, Goda et al. further teach, wherein the controller is further configured to apply voltage ramps in parallel to the first and second groups (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0088).
Regarding claim 19, Goda et al. further teach, further comprising sensing circuitry configured to read the memory cells of the first and second groups, wherein the controller is further configured to determine, using the sensing circuitry, that at least a portion of the memory cells of the first and second groups switch (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0075).
Regarding claim 20, Goda et al. further teach, wherein the controller is further configured to apply voltage steps in parallel to the first and second groups (see Fig.1-10, paragraph 0025-0027, 0030-0044, 0047-0056, 0060-0080, 0087-0090).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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