DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on June 5, 2025 has been fully considered by the examiner.
Claim Objections
3. Claims 6, 13, and 19-20 are objected to because of the following informalities.
Claims 6, 13, and 19 each recite “using select chip terminate (SCT) packet” in line 3, which Examiner believes should recite “using a select chip terminate (SCT) packet.”
Claim 20 recites “The memory device of claim 15” in line 1, which Examiner believes should recite “The system of claim 15” because “the DQ circuitry activation command” referenced in claim 20, line 1, appears related to the memory sub-system controller of claim 15 (see line 8).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
5. Claims 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites the limitation, “to a die of a memory device” in lines 8-9, which is indefinite. For the purpose of this action, the aforementioned limitation shall be interpreted as “to [[a]] the die of [[a]] the memory device,” which finds antecedent basis in line 2. Claims 16-20 depend on claim 15.
Claim 15 recites the limitation, “a data (DQ) bus” in line 5, which is indefinite. For the purpose of this action, the aforementioned limitation shall be interpreted as “[[a]] the data (DQ) bus,” which finds antecedent basis in line 3.
Claim 15 recites the limitation, “data (DQ) circuitry” in line 9, which is indefinite. For the purpose of this action, the aforementioned limitation shall be interpreted as “the data (DQ) circuitry,” which finds antecedent basis in line 2.
Claim 15 recites the limitation, “a command address (CA) bus” in lines 5-6, which is indefinite. For the purpose of this action, the aforementioned limitation shall be interpreted as “[[a]] the command address (CA) bus,” which finds antecedent basis in lines 3-4.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1-2, 8-9, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Giduturi (US 20230335165 A1) in view of Ellis, et al (US 20190027210 A1), hereinafter Ellis.
Regarding independent claim 1, Giduturi teaches a memory device comprising:
a memory array (¶[0028]) comprising a plurality of dies (FIG. 3, 208; ¶[0003]); and
processing logic, operatively coupled with the memory array (FIG. 1, Control block 128, shown coupled to memory partitions; ¶[0036]), to perform operations (¶[0036]) comprising:
receiving a data (DQ) circuitry activation command (Abstract teaches “a wakeup message on the command line…”) via a command address (CA) bus (FIG. 8, CA; ¶[0094] teaches “bus 812 can include lines or paths for, among other things, a command/address (CA) signal”) operatively coupled with CA circuitry of the memory device (FIG. 8, 810, 808), wherein the DQ circuitry activation command comprises data identifying a die of the plurality of dies (Abstract teaches “a wakeup message on the command line comprises a chip identification”; see also FIG. 7, 708);
in response to receiving the DQ circuitry activation command, causing DQ circuitry of the die to transition from a standby state to an idle state;
receiving, via the CA bus, a data transaction initialization command of a data transaction; and
in response to receiving the data transaction initialization command, causing the DQ circuitry to transition from the idle state to an active state (While specific commands are not named (referenced more generically as, e.g., “standby exit command” or “opcode-based commands” in ¶[0025]), ¶[0097] teaches “the wakeup circuit 808 can listen to information on the bus 812, including the EX signal, for a particular data sequence that indicates a standby exit or standby entry and further indicates a chip ID corresponding to the particular die.” ¶[0096] further teaches “The wakeup circuit 808 can include always-active logic or processor circuitry that stays in an awake or active state while other circuitry in the same die is powered down or idle. The wakeup circuit 808 can listen to, e.g., the CA signal and the EX signal for instructions to wake the die.”).
Giduturi does not explicitly teach the power mode of DQ circuitry can be specifically controlled as described in the preceding limitations.
Ellis teaches the power mode of DQ circuitry can be specifically controlled (¶[0012] teaches “a ‘power down DQ’ (PDNDQ) command can specify only powering down the HSI portion coupled to DQ bus; ¶[0013] teaches “when the mode register is set to a certain value, only the transmitters and receivers associated with DQ bus 108 are powered down in response to a transition in the level of the PM signal 126, whereas the transmitters and receivers associated with CA bus 110 remain powered up”).
Regarding independent claim 8, Giduturi teaches a method comprising:
receiving, by processing device, a data (DQ) circuitry activation command (Abstract teaches “a wakeup message on the command line…”) via a command address (CA) bus (FIG. 8, CA; ¶[0094] teaches “bus 812 can include lines or paths for, among other things, a command/address (CA) signal”) operatively coupled with CA circuitry of a memory device (FIG. 8, 810, 808), wherein the DQ circuitry activation command comprises data identifying a die of the memory device (Abstract teaches “a wakeup message on the command line comprises a chip identification”; see also FIG. 7, 708);
in response to receiving the DQ circuitry activation command, causing, by the processing device, DQ circuitry of the memory device to transition from a standby state to an idle state;
receiving, by the processing device via the CA bus, a data transaction initialization command of a data transaction; and
in response to receiving the data transaction initialization command, causing, by the processing device, the DQ circuitry to transition from the idle state to an active state (While specific commands are not named (referenced more generically as, e.g., “standby exit command” or “opcode-based commands” in ¶[0025]), ¶[0097] teaches “the wakeup circuit 808 can listen to information on the bus 812, including the EX signal, for a particular data sequence that indicates a standby exit or standby entry and further indicates a chip ID corresponding to the particular die.” ¶[0096] further teaches “The wakeup circuit 808 can include always-active logic or processor circuitry that stays in an awake or active state while other circuitry in the same die is powered down or idle. The wakeup circuit 808 can listen to, e.g., the CA signal and the EX signal for instructions to wake the die.”).
Giduturi does not explicitly teach the power mode of DQ circuitry can be specifically controlled as described in the preceding limitations.
Ellis teaches the power mode of DQ circuitry can be specifically controlled (¶[0012] teaches “a ‘power down DQ’ (PDNDQ) command can specify only powering down the HSI portion coupled to DQ bus; ¶[0013] teaches “when the mode register is set to a certain value, only the transmitters and receivers associated with DQ bus 108 are powered down in response to a transition in the level of the PM signal 126, whereas the transmitters and receivers associated with CA bus 110 remain powered up”).
Regarding independent claim 15, Giduturi teaches a system comprising:
a memory device (FIG. 1, 100) comprising a die (FIG. 3, one of dies 208; ¶[0003]), the die comprising data (DQ) circuitry (FIG. 1, I/O Interface 106; ¶[0031]) operatively coupled with a DQ bus (FIG. 1, 112; ¶[0031] teaches “a second bus 112 (or a signal path or another group of signal paths) that can, individually or in combination, allow for bidirectional transmission of signals, including, for example, data signals”) and command address (CA) circuitry operatively coupled with a CA bus (FIG. 8, CA; ¶[0094] teaches “bus 812 can include lines or paths for, among other things, a command/address (CA) signal”) and a chip enable pin (FIG. 5, CS; ¶[0062]); and
a memory sub-system controller (FIG. 1, Control block 128; ¶[0036]) operatively coupled with a data (DQ) bus (¶[0040] teaches “Data can be sent to and from the memory device 100 using the command and clocking signals discussed above, for example, by transmitting and receiving data signals through the input/output interface 106. More specifically, the data can be sent to or retrieved from the memory partitions 102 over a data path 130…”), a command address (CA) bus and a chip enable pin (FIG. 8, CA; ¶[0094] teaches “bus 812 can include lines or paths for, among other things, a command/address (CA) signal…a chip select (CS) signal…”; Command Decoder 810 is also shown in FIG. 1 (120) with signal paths 124 to Control Block 128), the memory sub-system controller comprising a processing device, operatively coupled with a memory, to perform operations (¶[0035] teaches Control Block 128 “provides decoding (e.g., row and/or column decoding), as well as other features, such as timing control and data control, to facilitate the execution of commands to and from the respective memory partition 102”) comprising:
causing a data transaction to be sent to the die via the CA bus, the data transaction comprising a data transaction initialization command to cause the DQ circuitry to transition from the idle state to an active state, and a data transaction termination command to cause the DQ circuitry to transaction from the active state to the standby state (¶[0085] teaches “a standby command protocol for the memory die stack 500 that can include a standby entry or standby exit command that is inserted in or used with other command messages on the shared command/address bus”).
Giduturi does not explicitly teach the power mode of DQ circuitry can be specifically controlled as described in the preceding limitations.
Ellis teaches the power mode of DQ circuitry can be specifically controlled (¶[0012] teaches “a ‘power down DQ’ (PDNDQ) command can specify only powering down the HSI portion coupled to DQ bus; ¶[0013] teaches “when the mode register is set to a certain value, only the transmitters and receivers associated with DQ bus 108 are powered down in response to a transition in the level of the PM signal 126, whereas the transmitters and receivers associated with CA bus 110 remain powered up”).
Ellis further teaches causing a DQ circuitry activation command to be sent, via the CA bus, to a die of a memory device to cause DQ circuitry of the die to transition from a standby state to an idle state (¶[0012-0016] teaches a power down DQ (PDNDQ) command (¶[0012]), an idle mode based on a value in a mode register (¶[0013]), and a receiver or transmitter can be enabled or disabled based on the power mode (¶[0014]); ¶[0034] and claim 8 further teach commands can affect mode registers and power modes; note Giduturi teaches an idle mode in ¶[0096], [0098], and [0100], but does not explicitly disclose how idle mode is entered).
Regarding claims 1, 8, and 15, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Ellis into the method of Giduturi to include selectively controlling the power mode of DQ circuitry. The ordinary artisan would have been motivated to modify Giduturi in the above manner for the purpose of reducing power without impacting the functionality of the CA bus (¶[0013]).
Regarding claim 2, Giduturi as modified by Ellis teaches the limitations of claim 1.
Giduturi further teaches causing the DQ circuitry to be placed in the standby state prior to receiving the DQ circuitry activation command (¶[0085] teaches “a standby command protocol for the memory die stack 500 that can include a standby entry or standby exit command that is inserted in or used with other command messages on the shared command/address bus”; it follows that a “standby exit command” is issued after a device has entered standby state).
Regarding claim 9, Giduturi as modified by Ellis teaches the limitations of claim 8.
Giduturi further teaches causing, by the processing device, the DQ circuitry to be placed in the standby state prior to receiving the DQ circuitry activation command (¶[0085] teaches “a standby command protocol for the memory die stack 500 that can include a standby entry or standby exit command that is inserted in or used with other command messages on the shared command/address bus”; it follows that a “standby exit command” is issued after a device has entered standby state).
Regarding claim 16, Giduturi as modified by Ellis teaches the limitations of claim 15.
Giduturi further teaches causing a command sequence to be sent to the die via the CA bus prior to causing the data transaction to be sent to the die via the CA bus (FIG. 6; ¶[0072] teaches “the first UI can include, and can lead with, an opcode field (OPCODE). The opcode field can include a multiple-bit (e.g., 5 bit) instruction designating a particular operation for the target device (e.g., read, write, etc.).” ¶[0073] teaches “message 602 can further include various additional operands (MA) that can include memory addresses, data, or other information”).
Regarding claim 17, Giduturi as modified by Ellis teaches the limitations of claim 16.
Giduturi further teaches causing another command to be sent to a second die of the memory device after causing the activation command to be sent to the die and prior to causing the command sequence to be sent to the die (¶[0018] in the present application appears to teach an activation command causes the target die to exit standby mode; Giduturi teaches in ¶[0093] “if the chip ID field of a stack standby exit command corresponds to the chip ID of the primary die” (“the die” of the claim), “then the primary die 410 can initiate exit for itself and, optionally, for one or more of the secondary dies” (“a second die” of the claim). At this time, “another command” of the format of FIG. 6, 602, with the chip ID (CID) for the “second die” may be sent).
Regarding claim 18, Giduturi as modified by Ellis teaches the limitations of claim 15.
Giduturi further teaches the operations further comprise at least one of:
sending, via the DQ bus, first data to be written to a memory array; or receiving, via the DQ bus, second data read out from the memory array (e.g., ¶[0085] teaches “The command decoder 810 can selectively respond to or execute commands (e.g., memory commands, such as read/write commands) received via the bus 812 when the command includes or uses the particular chip ID”; ¶[0031] teaches “a second bus 112 (or a signal path or another group of signal paths) that can, individually or in combination, allow for bidirectional transmission of signals, including, for example, data signals”; see also Ellis ¶[0012] and FIGS. 1-2).
8. Claims 3-7, 10-14, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Giduturi (US 20230335165 A1) in view of Ellis, et al (US 20190027210 A1), hereinafter Ellis, and further in view of Lee (US 20230326495 A1).
Regarding claim 3, Giduturi as modified by Ellis teaches the limitations of claim 1.
Giduturi further teaches causing first data received from a memory sub-system controller via the DQ bus to be written to the die (e.g., ¶[0085] teaches “The command decoder 810 can selectively respond to or execute commands (e.g., memory commands, such as read/write commands) received via the bus 812 when the command includes or uses the particular chip ID”; ¶[0031] teaches “a second bus 112 (or a signal path or another group of signal paths) that can, individually or in combination, allow for bidirectional transmission of signals, including, for example, data signals”; see also Ellis ¶[0012] and FIGS. 1-2).
Giduturi does not teach data is received after receiving the data transaction initialization command via the CA bus.
Lee teaches data is received after receiving the data transaction initialization command via the CA bus (¶[0050] teaches “After providing the second semiconductor apparatus 120 with the first selection chip enable command SCE1, the first semiconductor apparatus 110 may provide the second semiconductor apparatus 120 with the data DQ<0:7>”).
Regarding claim 4, Giduturi as modified by Ellis teaches the limitations of claim 1.
Giduturi further teaches causing second data to be read out from the die to a memory sub-system controller via the DQ bus (e.g., ¶[0085] teaches “The command decoder 810 can selectively respond to or execute commands (e.g., memory commands, such as read/write commands) received via the bus 812 when the command includes or uses the particular chip ID”; ¶[0031] teaches “a second bus 112 (or a signal path or another group of signal paths) that can, individually or in combination, allow for bidirectional transmission of signals, including, for example, data signals”; see also Ellis ¶[0012] and FIGS. 1-2).
Giduturi does not teach data is received after receiving the data transaction initialization command via the CA bus.
Lee teaches data is received after receiving the data transaction initialization command via the CA bus (¶[0050] teaches “After providing the second semiconductor apparatus 120 with the first selection chip enable command SCE1, the first semiconductor apparatus 110 may provide the second semiconductor apparatus 120 with the data DQ<0:7>”).
Regarding claim 10, Giduturi as modified by Ellis teaches the limitations of claim 8.
Giduturi further teaches causing, by the processing device, first data received from a memory sub-system controller via the DQ bus to be written to the die (e.g., ¶[0085] teaches “The command decoder 810 can selectively respond to or execute commands (e.g., memory commands, such as read/write commands) received via the bus 812 when the command includes or uses the particular chip ID”; ¶[0031] teaches “a second bus 112 (or a signal path or another group of signal paths) that can, individually or in combination, allow for bidirectional transmission of signals, including, for example, data signals”; see also Ellis ¶[0012] and FIGS. 1-2).
Giduturi does not teach data is received after receiving the data transaction initialization command via the CA bus.
Lee teaches data is received after receiving the data transaction initialization command via the CA bus (¶[0050] teaches “After providing the second semiconductor apparatus 120 with the first selection chip enable command SCE1, the first semiconductor apparatus 110 may provide the second semiconductor apparatus 120 with the data DQ<0:7>”).
Regarding claim 11, Giduturi as modified by Ellis teaches the limitations of claim 8.
Giduturi further teaches causing, by the processing device, second data to be read out to a memory sub-system controller via the DQ bus (e.g., ¶[0085] teaches “The command decoder 810 can selectively respond to or execute commands (e.g., memory commands, such as read/write commands) received via the bus 812 when the command includes or uses the particular chip ID”; ¶[0031] teaches “a second bus 112 (or a signal path or another group of signal paths) that can, individually or in combination, allow for bidirectional transmission of signals, including, for example, data signals”; see also Ellis ¶[0012] and FIGS. 1-2).
Giduturi does not teach data is received after receiving the data transaction initialization command via the CA bus.
Lee teaches data is received after receiving the data transaction initialization command via the CA bus (¶[0050] teaches “After providing the second semiconductor apparatus 120 with the first selection chip enable command SCE1, the first semiconductor apparatus 110 may provide the second semiconductor apparatus 120 with the data DQ<0:7>”).
Regarding claims 3-4 and 10-11, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Lee into the method of Giduturi to include a Selection Chip Enable (SCE) command. The ordinary artisan would have been motivated to modify Giduturi in the above manner for the purpose of initializing a data transfer via the DQ bus (Lee, ¶[0050], [0055]).
Regarding claim 5, Giduturi as modified by Ellis teaches the limitations of claim 1.
Giduturi does not teach receiving a data transaction termination command of the data transaction; and
in response to receiving the data transaction termination command, causing the DQ circuitry to transition from the active state to the standby state.
Lee teaches receiving a data transaction termination command of the data transaction; and
in response to receiving the data transaction termination command, causing the DQ circuitry to transition from the active state to the standby state (¶[0055] teaches “the first memory die DIE1 may enter a low power mode based on the first selection chip termination command SCT1. The low power mode may be a standby mode…”).
Regarding claim 12, Giduturi as modified by Ellis teaches the limitations of claim 8.
Giduturi does not teach receiving, by the processing device, a data transaction termination command of the data transaction; and
in response to receiving the data transaction termination command, causing, by the processing device, the DQ circuitry to transition from the active state to the standby state.
Lee teaches receiving, by the processing device, a data transaction termination command of the data transaction; and
in response to receiving the data transaction termination command, causing, by the processing device, the DQ circuitry to transition from the active state to the standby state (¶[0055] teaches “the first memory die DIE1 may enter a low power mode based on the first selection chip termination command SCT1. The low power mode may be a standby mode…”).
Regarding claim 19, Giduturi as modified by Ellis teaches the limitations of claim 15.
Giduturi does not teach the data transaction initialization command is implemented by a select chip enable (SCE) packet, and wherein the data transaction termination command is using select chip terminate (SCT) packet.
Lee teaches the data transaction initialization command is implemented by a select chip enable (SCE) packet, and wherein the data transaction termination command is using select chip terminate (SCT) packet (¶[0055] teaches “…the first selection chip enable command SCE1 and a first selection chip termination command SCT1”).
Regarding claim 20, Giduturi as modified by Ellis teaches the limitations of claim 15.
Giduturi does not teach the DQ circuitry activation command, the data transaction initialization command and the data transaction termination command are implemented using a Separate Command Address (SCA) protocol (¶[0055] teaches “…the first selection chip enable command SCE1 and a first selection chip termination command SCT1” and “when the first semiconductor apparatus 110 provides the first selection chip disable command SCD1, the first memory die DIE1 may be in a ready state, not the low power mode, and maintain an activated state to perform another operation”; ¶[0004] teaches SCA protocol).
Regarding claims 5, 12, and 19-20, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Lee into the method of Giduturi to include a Selection Chip Termination (SCT) command to enter a low-power mode. The ordinary artisan would have been motivated to modify Giduturi in the above manner for the purpose of reducing command overhead and improving performance of a semiconductor system (Lee, ¶[0055]).
Regarding claim 6, Giduturi as modified by Ellis and Lee teaches the limitations of claim 5.
Lee further teaches the data transaction initialization command is implemented by a select chip enable (SCE) packet, and wherein the data transaction termination command is using select chip terminate (SCT) packet (¶[0055] teaches “…the first selection chip enable command SCE1 and a first selection chip termination command SCT1”).
Regarding claim 7, Giduturi as modified by Ellis and Lee teaches the limitations of claim 5.
Lee further teaches the DQ circuitry activation command, the data transaction initialization command and the data transaction termination command are implemented using a Separate Command Address (SCA) protocol (¶[0004]).
Regarding claim 13, Giduturi as modified by Ellis and Lee teaches the limitations of claim 12.
Lee further teaches the data transaction initialization command is implemented by a select chip enable (SCE) packet, and wherein the data transaction termination command is using select chip terminate (SCT) packet (¶[0055] teaches “…the first selection chip enable command SCE1 and a first selection chip termination command SCT1”).
Regarding claim 14, Giduturi as modified by Ellis and Lee teaches the limitations of claim 12.
Lee further teaches the DQ circuitry activation command, the data transaction initialization command and the data transaction termination command are implemented using a Separate Command Address (SCA) protocol (¶[0055] teaches “…the first selection chip enable command SCE1 and a first selection chip termination command SCT1” and “when the first semiconductor apparatus 110 provides the first selection chip disable command SCD1, the first memory die DIE1 may be in a ready state, not the low power mode, and maintain an activated state to perform another operation”; ¶[0004] teaches SCA protocol).
Conclusion
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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