DETAILED ACTION
This action is responsive to the following communications: the Application filed on January 28, 2025, the provisional application No. 63/626,458 filed on January 29, 2024, and the Information Disclosure Statement filed on July 30, 2025.
Claims 1-20 are pending. Claims 1, 10 and 20 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on July 30, 2025. This IDS has been considered.
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0019], line 1, “the forgoing examples” should be –the foregoing examples--.
In paragraph [0020], line 17, “DFCB sensing” should be --DCFB sensing--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7 and 17 recite “for a first word line number at a first read level, the partial block offset table specifies a first read-level voltage offset for an inner word line and a second read-level voltage offset for a boundary word line, wherein the second read-level voltage offset is higher than the first read- level voltage offset”. The term “higher” is unclear in the context of the claimed read-level voltage offsets. The specification’s Table 1 provides example read-level voltage offsets for inner word line and boundary word lines, and many of the listed values are negative. For example, for the last WL < 57 at R1, the inner word line offset is -13, while the boundary word line offset is -23. Numerically, -23 is lower than -13, but in absolute magnitude, the boundary word line offset has a greater magnitude than the inner word line offset. Therefore, it is unclear whether the claim phrase “the second read-level voltage offset is higher than the first read- level voltage offset” means the second offset is numerically greater than the first offset or the second offset has a greater absolute magnitude than the first offset. Because the claim does not make clear which meaning is intended, the scope of claims 7 and 17 is indefinite.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20230393991) in view of Parthasarathy et al. (US 20210103389) and further in view of Nguyen et al. (US20240029801).
Regarding independent claim 1, Chang et al. disclose a memory sub-system [Fig. 1: 110] comprising:
a memory device [Fig. 1: 130, para. 37-38]; and
a processing device [Fig. 1: 115], operatively coupled with the memory device to perform operations [a memory sub-system controller 115 can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, para. 42] comprising:
receiving a command to read data stored in a block of the memory device [Fig. 6: step 610, the processing logic receives a read command specifying a logical address from a host system, para. 70];
determining the block is a partial block based on the block having one or more unprogrammed pages [Fig. 6: step 630, to determine that the physical block is partially programmed, the processing logic can identify an indicator (e.g., a full block indicator) that indicates whether the physical block is fully programmed, para. 72. When every wordline in a block is programmed, the block is fully programmed and can be referred to as a full block. A partially programmed block (or a partial block) refers to a block in which not every wordline has been programmed, para. 19];
based on the block being a partial block, accessing a partial block offset table comprising a mapping between word line numbers and read-level voltage offsets for partial blocks [the processing logic can maintain a number of threshold voltage offset tables, each table corresponding to a wordline group, a media state metric value (e.g., a program/erase cycle count), and/or whether or not the wordline is a boundary wordline. If the wordline is the boundary wordline, the processing logic identifies a first voltage threshold offset table. If the wordline is not the boundary wordline for the block, the processing logic identifies a second voltage threshold offset set, para. 74. Each table 504, 506 lists read offset levels for each bin number (bin 0 through bin 7) and read level (e.g., TLC 1 through TLC 7), para. 64];
determining a word line type [Chang et al. disclose the data retention tests to determine whether the data is stored in a boundary wordline or an inner wordline, and/or the difference between the boundary wordline and the wordline storing the data, para. 30 as well as para. 65];
determining, from the partial block offset table, a set of first read-level voltage offsets for the block based on one or more word line numbers associated with the last written page and the word line type [Chang et al. disclose selecting the appropriate sub-BFEA offset table based on whether data is stored in a boundary or inner wordline, difference from boundary wordline and wordline group, then identifying the read offset based on bin number and voltage read level, para. 64-68 as well as para. 74-75]; and
applying the set of first read-level voltage offsets to the block [the adaptive BFEA component 113 can then additively apply the identified threshold voltage offset to the base voltage read level in order to perform the requested read operation, para. 68 as well as para. 76-77].
However, Chang et al are silent with respect to identifying a last written page in the block;
determining a word line type based on the last written page; and
performing a read-level voltage calibration process that includes determining a second set of read-level voltage offsets for the block based on a number of failing bits read from the block.
Parthasarathy et al. teach identifying a last written page in the block and determining a word line type based on the last written page [the last written page information 235 can provide a status of pages last written to partially written blocks, which can include identifiers (e.g., page numbers) of the last written pages and may also indicate a completion status of the last written page (e.g., whether the page belongs to a group of partially programmed cells, or whether the page is fully programmed), para. 28].
Furthermore, Nguyen et al. teach performing a read-level voltage calibration process that includes determining a second set of read-level voltage offsets for the block based on a number of failing bits read from the block [Fig. 7: step 708, the controller performs a read voltage calibration that based on the failed bit count may return a second read voltage level adjustment value, para. 96].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Parthasarathy et al. and Nguyen et al. to the teaching of Chang et al. such that modifying the partial block offset technique of Chang et al. as informed by last written page teaching of Parthasarathy et al. to further use the read calibration of Nguyen et al. A person having ordinary skill in the art would have been motivated to use the partial block offset as the initial read level correction and then refine it using CFByte calibration to reduce read errors and improve read accuracy.
Regarding claim 2, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 1.
Chang et al. disclose wherein the operations comprise performing a first read operation at the block with the first set of read-level voltage offsets applied to the block [the adaptive BFEA component 113 can then additively apply the identified threshold voltage offset to the base voltage read level in order to perform the requested read operation, para. 68 as well as para. 76-77].
Furthermore, Nguyen et al. teach the operations comprise:
determining the number of failing bits read from the block based on the first read operation [the memory device may, upon performing a read strobe, return the failed byte count (CFByte). The failed byte count reflects the number of bytes in the sensed data that have at least one non-conducting bitline, para. 51];
determining the second set of read-level voltage offsets based on the number of failing bits read from the block [Fig. 7: step 708, the controller performs a read voltage calibration that based on the failed bit count may return a second read voltage level adjustment value, para. 96]; and
performing a second read operation with the second set of read-level voltage offsets applied to read the data from the block [Fig. 7: step 712, the controller performs re-reading data using the adjusted read voltage level based on the second read voltage level adjustment value, para. 96-98].
Regarding claim 3, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 1.
Furthermore, Nguyen et al. disclose wherein the read-level voltage calibration process comprises performing digital count fail byte (DCFB) sensing [the controller performs a read voltage calibration based on the first chosen metric (e.g., reflecting a failed byte count, CFByte), para. 95. CFByte is determined based on the number of bytes in the sensed data that have at least one non-conducting bitline, para. 104].
Regarding claim 4, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 1.
Furthermore, Chang et al. disclose wherein determining the word line type comprises determining whether the last written page corresponds to an inner word line or a boundary word line [Chang et al. disclose the data retention tests to determine whether the data is stored in a boundary wordline or an inner wordline, and/or the difference between the boundary wordline and the wordline storing the data, para. 30 as well as para. 65].
Regarding claim 5, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 4.
Furthermore, Parthasarathy et al. disclose wherein determining whether the last written page corresponds to an inner word line or a boundary word line is based on a page map, the page map identifying pages in the block that have been programmed [the last written page information 235 can provide a status of pages last written to partially written blocks, which can include identifiers (e.g., page numbers) of the last written pages and may also indicate a completion status of the last written page (e.g., whether the page belongs to a group of partially programmed cells, or whether the page is fully programmed), para. 28].
Regarding claim 6, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 3.
Furthermore, Chang et al. disclose wherein the partial block offset table specifies different read-level voltage offsets for different word line types [Chang et al. disclose multiple sub-BFEA offset tables for a boundary wordline and for an inner wordline, para. 29 as well as para. 65].
Regarding claim 7, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 3.
Furthermore, Chang et al. disclose wherein, for a first word line number at a first read level, the partial block offset table specifies a first read-level voltage offset for an inner word line and a second read-level voltage offset for a boundary word line, wherein the second read-level voltage offset is higher than the first read- level voltage offset [Chang et al. teach the sub-BFEA offset table for a boundary wordline differs from the sub-BFEA offset table for an inner wordline because the threshold voltage shift associated with the boundary wordline of a partially programmed block tends to be more severe than the threshold voltage shift associated with an inner wordline of the partially programmed block, para. 29 as well as para. 65].
Regarding claim 8, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 1.
Furthermore, Parthasarathy et al. disclose wherein determining the last written page comprises accessing a page map identifying pages in the block that have been programmed [the last written page information 235 can provide a status of pages last written to partially written blocks, which can include identifiers (e.g., page numbers) of the last written pages and may also indicate a completion status of the last written page (e.g., whether the page belongs to a group of partially programmed cells, or whether the page is fully programmed), para. 28].
Regarding claim 9, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 1.
Furthermore, Chang et al. disclose wherein each row of the partial block offset table corresponds to one or more word line numbers and each row includes a set of read level voltage offsets, the set of read level voltage offsets in each row including a read level voltage offset for each read level [Chang et al. disclose tables listing read offset levels for each bin number (bin 0 through bin 7) and read level (e.g., TLC 1 through TLC 7), para. 64. Chang et al. also disclose the appropriate additional sub-BFEA offset table can be identified based on the sub-BFEA parameters, such as whether the data is stored in a boundary wordline or an inner wordline, the difference between the boundary wordline and the wordline storing the data, and/or the wordline group of the wordline, para. 67. Therefore, the row corresponds to one and more word line numbers is an obvious table variation because Chang et al. already uses the wordline group of the wordline as a table selection parameter].
Regarding independent claim 10, Chang et al. disclose a method [see Fig. 6] comprising:
receiving a command to read data stored in a block of a memory device [Fig. 6: step 610, the processing logic receives a read command specifying a logical address from a host system, para. 70];
based on the block being a partial block, accessing a partial block offset table comprising a mapping between word line numbers and read-level voltage offsets for partial blocks [the processing logic can maintain a number of threshold voltage offset tables, each table corresponding to a wordline group, a media state metric value (e.g., a program/erase cycle count), and/or whether or not the wordline is a boundary wordline. If the wordline is the boundary wordline, the processing logic identifies a first voltage threshold offset table. If the wordline is not the boundary wordline for the block, the processing logic identifies a second voltage threshold offset set, para. 74. Each table 504, 506 lists read offset levels for each bin number (bin 0 through bin 7) and read level (e.g., TLC 1 through TLC 7), para. 64];
determining a word line type [Chang et al. disclose the data retention tests to determine whether the data is stored in a boundary wordline or an inner wordline, and/or the difference between the boundary wordline and the wordline storing the data, para. 30 as well as para. 65];
determining, from the partial block offset table, a set of first read-level voltage offsets for the block based on one or more word line numbers associated with the last written page and the word line type [Chang et al. disclose selecting the appropriate sub-BFEA offset table based on whether data is stored in a boundary or inner wordline, difference from boundary wordline and wordline group, then identifying the read offset based on bin number and voltage read level, para. 64-68 as well as para. 74-75]; and
applying the set of first read-level voltage offsets to the block [the adaptive BFEA component 113 can then additively apply the identified threshold voltage offset to the base voltage read level in order to perform the requested read operation, para. 68 as well as para. 76-77].
However, Chang et al are silent with respect to identifying a last written page in the block;
determining a word line type based on the last written page; and
performing a read-level voltage calibration process that includes determining a second set of read-level voltage offsets for the block based on a number of failing bits read from the block.
Parthasarathy et al. teach identifying a last written page in the block and determining a word line type based on the last written page [the last written page information 235 can provide a status of pages last written to partially written blocks, which can include identifiers (e.g., page numbers) of the last written pages and may also indicate a completion status of the last written page (e.g., whether the page belongs to a group of partially programmed cells, or whether the page is fully programmed), para. 28].
Furthermore, Nguyen et al. teach performing a read-level voltage calibration process that includes determining a second set of read-level voltage offsets for the block based on a number of failing bits read from the block [Fig. 7: step 708, the controller performs a read voltage calibration that based on the failed bit count may return a second read voltage level adjustment value, para. 96].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Parthasarathy et al. and Nguyen et al. to the teaching of Chang et al. such that modifying the partial block offset technique of Chang et al. as informed by last written page teaching of Parthasarathy et al. to further use the read calibration of Nguyen et al. A person having ordinary skill in the art would have been motivated to use the partial block offset as the initial read level correction and then refine it using CFByte calibration to reduce read errors and improve read accuracy.
Regarding claim 11, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 10.
Furthermore, Chang et al. disclose comprising determining the block is a partial block based on the block having one or more unprogrammed pages [Fig. 6: step 630, to determine that the physical block is partially programmed, the processing logic can identify an indicator (e.g., a full block indicator) that indicates whether the physical block is fully programmed, para. 72. When every wordline in a block is programmed, the block is fully programmed and can be referred to as a full block. A partially programmed block (or a partial block) refers to a block in which not every wordline has been programmed, para. 19].
Regarding claim 12, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 10.
Chang et al. disclose comprising performing a first read operation at the block with the first set of read-level voltage offsets applied to the block [the adaptive BFEA component 113 can then additively apply the identified threshold voltage offset to the base voltage read level in order to perform the requested read operation, para. 68 as well as para. 76-77].
Furthermore, Nguyen et al. teach comprising:
determining the number of failing bits read from the block based on the first read operation [the memory device may, upon performing a read strobe, return the failed byte count (CFByte). The failed byte count reflects the number of bytes in the sensed data that have at least one non-conducting bitline, para. 51];
determining the second set of read-level voltage offsets based on the number of failing bits read from the block [Fig. 7: step 708, the controller performs a read voltage calibration that based on the failed bit count may return a second read voltage level adjustment value, para. 96]; and
performing a second read operation with the second set of read-level voltage offsets applied to read the data from the block [Fig. 7: step 712, the controller performs re-reading data using the adjusted read voltage level based on the second read voltage level adjustment value, para. 96-98].
Regarding claim 13, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 10.
Furthermore, Nguyen et al. disclose wherein the read-level voltage calibration process comprises performing digital count fail byte (DCFB) sensing [the controller performs a read voltage calibration based on the first chosen metric (e.g., reflecting a failed byte count, CFByte), para. 95. CFByte is determined based on the number of bytes in the sensed data that have at least one non-conducting bitline, para. 104].
Regarding claim 14, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 10.
Furthermore, Chang et al. disclose wherein determining the word line type comprises determining whether the last written page corresponds to an inner word line or a boundary word line [Chang et al. disclose the data retention tests to determine whether the data is stored in a boundary wordline or an inner wordline, and/or the difference between the boundary wordline and the wordline storing the data, para. 30 as well as para. 65].
Regarding claim 15, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 14.
Furthermore, Parthasarathy et al. disclose wherein determining whether the last written page corresponds to an inner word line or a boundary word line is based on a page map, the page map identifying pages in the block that have been programmed [the last written page information 235 can provide a status of pages last written to partially written blocks, which can include identifiers (e.g., page numbers) of the last written pages and may also indicate a completion status of the last written page (e.g., whether the page belongs to a group of partially programmed cells, or whether the page is fully programmed), para. 28].
Regarding claim 16, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 14.
Furthermore, Chang et al. disclose wherein the partial block offset table specifies different read-level voltage offsets for different word line types [Chang et al. disclose multiple sub-BFEA offset tables for a boundary wordline and for an inner wordline, para. 29 as well as para. 65].
Regarding claim 17, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 14.
Furthermore, Chang et al. disclose wherein, for a first word line number at a first read level, the partial block offset table specifies a first read-level voltage offset for an inner word line and a second read-level voltage offset for a boundary word line, wherein the second read-level voltage offset is higher than the first read- level voltage offset [Chang et al. teach the sub-BFEA offset table for a boundary wordline differs from the sub-BFEA offset table for an inner wordline because the threshold voltage shift associated with the boundary wordline of a partially programmed block tends to be more severe than the threshold voltage shift associated with an inner wordline of the partially programmed block, para. 29 as well as para. 65].
Regarding claim 18, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 10.
Furthermore, Parthasarathy et al. disclose wherein determining the last written page comprises accessing a page map identifying pages in the block that have been programmed [the last written page information 235 can provide a status of pages last written to partially written blocks, which can include identifiers (e.g., page numbers) of the last written pages and may also indicate a completion status of the last written page (e.g., whether the page belongs to a group of partially programmed cells, or whether the page is fully programmed), para. 28].
Regarding claim 19, Chang et al. in combination with Parthasarathy et al. and Nguyen et al. teach the limitations with respect to claim 10.
Furthermore, Chang et al. disclose wherein each row of the partial block offset table corresponds to one or more word line numbers and each row includes a set of read level voltage offsets, the set of read level voltage offsets in each row including a read level voltage offset for each read level [Chang et al. disclose tables listing read offset levels for each bin number (bin 0 through bin 7) and read level (e.g., TLC 1 through TLC 7), para. 64. Chang et al. also disclose the appropriate additional sub-BFEA offset table can be identified based on the sub-BFEA parameters, such as whether the data is stored in a boundary wordline or an inner wordline, the difference between the boundary wordline and the wordline storing the data, and/or the wordline group of the wordline, para. 67. Therefore, the row corresponds to one and more word line numbers is an obvious table variation because Chang et al. already uses the wordline group of the wordline as a table selection parameter].
Regarding independent claim 20, Chang et al. disclose a computer-readable storage medium [Fig. 8: 800] comprising instructions that, when executed by a processing device [para. 87-92], configure the processing device to perform operations comprising:
receiving a command to read data stored in a block of a memory device [Fig. 6: step 610, the processing logic receives a read command specifying a logical address from a host system, para. 70];
determining the block has one or more unprogrammed pages [Fig. 6: step 630, to determine that the physical block is partially programmed, the processing logic can identify an indicator (e.g., a full block indicator) that indicates whether the physical block is fully programmed, para. 72. When every wordline in a block is programmed, the block is fully programmed and can be referred to as a full block. A partially programmed block (or a partial block) refers to a block in which not every wordline has been programmed, para. 19];
based on determining the block has one or more unprogrammed pages, accessing a partial block offset table comprising a mapping between word line numbers and read-level voltage offsets for partial blocks [the processing logic can maintain a number of threshold voltage offset tables, each table corresponding to a wordline group, a media state metric value (e.g., a program/erase cycle count), and/or whether or not the wordline is a boundary wordline. If the wordline is the boundary wordline, the processing logic identifies a first voltage threshold offset table. If the wordline is not the boundary wordline for the block, the processing logic identifies a second voltage threshold offset set, para. 74. Each table 504, 506 lists read offset levels for each bin number (bin 0 through bin 7) and read level (e.g., TLC 1 through TLC 7), para. 64];
determining a word line type [Chang et al. disclose the data retention tests to determine whether the data is stored in a boundary wordline or an inner wordline, and/or the difference between the boundary wordline and the wordline storing the data, para. 30 as well as para. 65];
determining, from the partial block offset table, a set of first read-level voltage offsets for the block based on one or more word line numbers associated with the last written page and the word line type [Chang et al. disclose selecting the appropriate sub-BFEA offset table based on whether data is stored in a boundary or inner wordline, difference from boundary wordline and wordline group, then identifying the read offset based on bin number and voltage read level, para. 64-68 as well as para. 74-75]; and
applying the set of first read-level voltage offsets to the block [the adaptive BFEA component 113 can then additively apply the identified threshold voltage offset to the base voltage read level in order to perform the requested read operation, para. 68 as well as para. 76-77].
However, Chang et al are silent with respect to determining a word line type based on a last written page; and
performing a read-level voltage calibration process that includes determining a second set of read-level voltage offsets for the block based on a number of failing bits read from the block.
Parthasarathy et al. teach determining a word line type based on a last written page [the last written page information 235 can provide a status of pages last written to partially written blocks, which can include identifiers (e.g., page numbers) of the last written pages and may also indicate a completion status of the last written page (e.g., whether the page belongs to a group of partially programmed cells, or whether the page is fully programmed), para. 28].
Furthermore, Nguyen et al. teach performing a read-level voltage calibration process that includes determining a second set of read-level voltage offsets for the block based on a number of failing bits read from the block [Fig. 7: step 708, the controller performs a read voltage calibration that based on the failed bit count may return a second read voltage level adjustment value, para. 96].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Parthasarathy et al. and Nguyen et al. to the teaching of Chang et al. such that modifying the partial block offset technique of Chang et al. as informed by last written page teaching of Parthasarathy et al. to further use the read calibration of Nguyen et al. A person having ordinary skill in the art would have been motivated to use the partial block offset as the initial read level correction and then refine it using CFByte calibration to reduce read errors and improve read accuracy.
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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