DETAILED ACTION
This action is responsive to the application filed January 29, 2025. Claims 1-20 are pending. Claims 1, 12, and 20 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDS) filed on February 4, 2025, and April 21, 2026. These IDS have been considered.
Claim Rejections - 35 USC § 112 – written description
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3, 7, 14 and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 3 and 14, claim 3 recites that “a sense amplifier capacitor integration time is modified to provide the different program-verify levels.” Claim 14 recites the corresponding method step of “modifying a sense amplifier capacitor integration time to provide the different program-verify levels.”
The specification contains the following statements at paragraphs [0053]–[0056]:
“In another embodiment, modification of the sense amplifier (SA) capacitor integration time may be used instead of modification of VCGR to reduce the write latency, while keeping the double number of verify levels to accommodate for best BER balancing. Modulating capacitor integration time may produce results similar to VCGR modulation without the need to actually modify VCGR, which can incur a higher latency. Using the same VCGR with multiple capacitor integration times can result in faster verification time, leading to a higher programming speed.”
“These verify levels can be adjusted directly through VCGR or indirectly through SA capacitor integration time modulation.”
“the controller 102 … performs a fast QPW step to modify the capacitor integration time … performs a slow QPW step to modify the capacitor integration time …”
(and corresponding left-cell / right-cell steps in the description of Figure 6).
This disclosure does not demonstrate that the inventors were in possession of the full scope of the claimed subject matter at the time of filing. In particular, the specification fails to describe:
Any structure of the sense amplifier or identification of the capacitor whose integration time is being modified;
Any circuit elements, control signals, or mechanism by which the integration time is actually changed;
The electrical relationship that allows a change in capacitor integration time to produce an effect equivalent to a different program-verify level or VCGR shift; and
Any algorithm, timing sequence, or concrete implementation that would enable a person of ordinary skill in the art to perform the claimed modification.
A mere statement of a desired result or desired capability, without a description of how that result is achieved, is insufficient to satisfy the written description requirement the full breadth of the functional limitations recited in Claims 3 and 14.
Under the rationale of In re Steele, prior-art consideration of claims 3 and 14 will be deferred pending resolution of the written-description rejection under 35 U.S.C. § 112(a).
Regarding claims 7 and 18, claim 7 recites that the one or more processors are further configured to “move data in response to determining that the BER balancing was unsuccessful.” Claim 18 recites the corresponding method step of “moving data in response to determining that balancing the bit error rate was unsuccessful.”
The specification contains only the following high-level statement at paragraph [0062]: “In another embodiment, when the BER is not fully balanced between the logical pages, data that is more important may be written to the ‘safer’ logical pages. This data can include, for example, a firmware header, important metadata, security keys, computation results, and other objects that are more important than the regular data.”
This disclosure does not demonstrate that the inventors were in possession of the full scope of the claimed subject matter at the time of filing. In particular, the specification fails to describe:
Any concrete criteria, metric, threshold, or process by which the system determines that BER balancing “was unsuccessful”;
How or when that determination is performed;
Which data is selected for movement, the basis for selecting that data, or the destination (“safer”) locations to which the data is moved; and
Any corresponding structure, algorithm, or firmware/controller implementation that performs the claimed “move data” step in response to the determination.
A mere statement of a desired result or desired capability, without a description of how that result is achieved, is insufficient to satisfy the written description requirement for the full breadth of the functional limitations recited in Claims 7 and 18.
Under the rationale of In re Steele, prior-art consideration of claims 7 and 18 will be deferred pending resolution of the written-description rejection under 35 U.S.C. § 112(a).
Claim Rejections - 35 USC § 112 - indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites that the one or more processors are further configured to “set the program-verify levels in the first and second sets of memory cells based on a determined soft bit efficiency value.” Claim 19 recites the corresponding method limitation of “setting the program-verify levels in the first and second sets of memory cells based on a determined soft bit efficiency value.”
The specification discusses the general concept of soft-bit efficiency in paragraphs [0061]–[0063], noting that certain entangled pages have lower soft-bit sensing efficiency / reduced correction capability and that BER balancing can be adjusted to favor those pages. However, the specification does not define or describe:
What constitutes a “soft bit efficiency value”;
How that value is measured, calculated, or otherwise “determined”;
The units, scale, or quantitative meaning of the value; or
The specific relationship or mapping between any such value and the selection or adjustment of the program-verify levels.
As a result, a person of ordinary skill in the art cannot determine the metes and bounds of the claim with reasonable certainty. The phrase “based on a determined soft bit efficiency value” is purely functional and leaves the scope of the limitation unclear.
In accordance with MPEP 2173.06, to promote compact prosecution, the phrase "based on a determined soft bit efficiency value" will be interpreted for purposes of prior art as "the program-verify levels applied to the first and second sets of memory cells are set or adjusted in some manner that takes into account relative differences in decoding quality or correction capability among the logical pages". This interpretation is the broadest reasonable interpretation consistent with the limited disclosure in para. [0061] – [0063] of the specification.
Claim Interpretation – means plus function
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Such claim limitations are in claim 20 (e.g., "…and means for bit error rate (BER) balancing by using different program-verify levels to verify programming memory cells in the first and second sets of memory cells when storing a non-integer number of bits in each of the programmed memory cells.")
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 8, 10-13, 15-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shibata et al. (US 20190259458; "Shibata") in view of Chen et al. (US 20050276101; "Chen") as supported by Dong et al. ("Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC NAND Flash Memory"; "Dong").
Regarding independent claim 1, Shibata discloses a data storage device comprising:
a memory comprising a wordline (Fig. 2 where it depicts WL0 for example),
wherein the wordline comprises first and second sets of memory cells (Abstr. "a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells");
and one or more processors (Fig. 1, memory controller 20), individually or in combination, configured to:
program memory cells in the first and second sets of memory cells to store a non-integer number of bits in each of the programmed memory cells (Fig. 9. See also para. 127; "Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.);
Shibata discloses the first and second sets of memory cells and the storage of a non-integer number of bits by a combination of their threshold voltages but is silent with respect to performing BER balancing using different program-verify levels in the first and second sets of memory cells.
However, Chen teaches by using different program-verify levels in the first and second sets of memory cells (Fig. 2. See also para. 49; " The bit lines are also divided into even bit lines (BLe) and odd bit lines (BLo)". Further, Fig. 14B and para. 79; "The use of the second programming pass (2ndPassWrite) procedure is shown, as well as different verify levels for the first pass (61) and for the second pass (64)".).
Shibata and Chen combined disclose the memory device using different program-verify levels for the different cell groups on a word line structure. Chen discloses the purpose as minimizing the effect of charge coupling between adjacent floating gates (the Yupin effect) but does not explicitly mention BER.
However, Dong directly supports the link between cell-to-cell interference - the Yupin effect, and BER: and perform bit error rate (BER) balancing (Abstr. "Cell-to-cell interference has been well recognized as a major noise source responsible for raw-memory-storage reliability degradation." See also pg. 2721, Sect II(C), col 2; "The results also suggest that, during the memory read operations, sensing reference voltages for even and odd cells should be configured differently in order to minimize sensing BERs in the presence of significant cell-to-cell interference.).
Shibata, Chen and Dong are from the same field of endeavor as applicant's invention directed to optimizing non-volatile memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor memory that stores a non-integer number of bits using the combination of threshold voltages of first and second memory cells as taught by Shibata, with the application of different program-verify levels to different groups of cells (odd/even) on a word line structure in order to minimize the inter-cell floating-gate coupling – BER balancing, as taught by Chen. As evidenced by Dong, cell-to-cell interference is a major noise source that distorts threshold-voltage distributions and is responsible for storage reliability degradation and elevated bit error rates.
Doing so would improve the reliability of the paired-cell multi-bit storage by managing the resulting bit error rates between cells.
Regarding independent claim 12, Shibata discloses in a data storage device comprising
a memory comprising a wordline, wherein the wordline comprises first and second sets of memory cells (Abstr. "a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells"),
a method comprising:
programming a fractional number of bits per memory cell in memory cells in the first and second sets of memory cells (Fig. 9. See also para. 127; "Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.);
Shibata discloses the first and second sets of memory cells and the storage of a non-integer number of bits by a combination of their threshold voltages but is silent with respect to performing BER balancing using different program-verify levels in the first and second sets of memory cells.
However, Chen teaches and using different program-verify levels in the first and second sets of memory cells to balance a bit error rate between the first and second sets of memory cells. (Fig. 2. See also para. 49; " The bit lines are also divided into even bit lines (BLe) and odd bit lines (BLo)". Further, Fig. 14B and para. 79; "The use of the second programming pass (2ndPassWrite) procedure is shown, as well as different verify levels for the first pass (61) and for the second pass (64)".).
Shibata and Chen combined disclose the memory device using different program-verify levels for the different cell groups on a word line structure. Chen discloses the purpose as minimizing the effect of charge coupling between adjacent floating gates (the Yupin effect) but does not explicitly mention BER.
However, Dong directly supports the link between cell-to-cell interference - the Yupin effect, and BER: and perform bit error rate (BER) balancing (Abstr. "Cell-to-cell interference has been well recognized as a major noise source responsible for raw-memory-storage reliability degradation." See also pg. 2721, Sect II(C), col 2; "The results also suggest that, during the memory read operations, sensing reference voltages for even and odd cells should be configured differently in order to minimize sensing BERs in the presence of significant cell-to-cell interference.).
Shibata, Chen and Dong are from the same field of endeavor as applicant's invention directed to optimizing non-volatile memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor memory that stores a non-integer number of bits using the combination of threshold voltages of first and second memory cells as taught by Shibata, with the application of different program-verify levels to different groups of cells (odd/even) on a word line structure in order to minimize the inter-cell floating-gate coupling – BER balancing, as taught by Chen. As evidenced by Dong, cell-to-cell interference is a major noise source that distorts threshold-voltage distributions and is responsible for storage reliability degradation and elevated bit error rates.
Regarding independent claim 20, as noted above, the means plus function structure of this claim is being interpreted under 35 U.S.C. § 112(f). Corresponding structure is found in the specification at para. [0051] – [ 0054] and the claim is therefore limited to that corresponding structure and equivalents thereof.
Shibata discloses a data storage device comprising:
a memory comprising first and second sets of memory cells (Fig. 2, see also Abstr. "a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells");
Shibata discloses the first and second sets of memory cells and the storage of a non-integer number of bits by a combination of their threshold voltages but is silent with respect to performing BER balancing using different program-verify levels in the first and second sets of memory cells.
However, Chen teaches and means for bit error rate (BER) balancing by using different program-verify levels to verify programming memory cells in the first and second sets of memory cells when storing a non-integer number of bits in each of the programmed memory cells. (Fig. 2. See also para. 49; " The bit lines are also divided into even bit lines (BLe) and odd bit lines (BLo)". Further, Fig. 14B and para. 79; "The use of the second programming pass (2ndPassWrite) procedure is shown, as well as different verify levels for the first pass (61) and for the second pass (64)".).
Shibata and Chen combined disclose the memory device using different program-verify levels for the different cell groups on a word line structure. Chen discloses the purpose as minimizing the effect of charge coupling between adjacent floating gates (the Yupin effect) but does not explicitly mention BER.
However, Dong directly supports the link between cell-to-cell interference - the Yupin effect, and BER: and perform bit error rate (BER) balancing (Abstr. "Cell-to-cell interference has been well recognized as a major noise source responsible for raw-memory-storage reliability degradation." See also pg. 2721, Sect II(C), col 2; "The results also suggest that, during the memory read operations, sensing reference voltages for even and odd cells should be configured differently in order to minimize sensing BERs in the presence of significant cell-to-cell interference.).
Shibata, Chen and Dong are from the same field of endeavor as applicant's invention directed to optimizing non-volatile memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor memory that stores a non-integer number of bits using the combination of threshold voltages of first and second memory cells as taught by Shibata, with the application of different program-verify levels to different groups of cells (odd/even) on a word line structure in order to minimize the inter-cell floating-gate coupling – BER balancing, as taught by Chen. As evidenced by Dong, cell-to-cell interference is a major noise source that distorts threshold-voltage distributions and is responsible for storage reliability degradation and elevated bit error rates.
Regarding claims 2 and 13, Shibata and Chen as supported by Dong disclose the limitations of claim 1 and 12 respectively.
As applied, Chen further discloses wherein different voltage-to-control-gate (VCGR) shifts are used to provide the different program-verify levels (Fig. 13(A). See also para. 78; "state then occurs by using a threshold voltage verify level 64 that is higher than the first verify level 61 and positioned within the distribution 62.").
Regarding claims 4 and 15, Shibata and Chen as supported by Dong disclose the limitations of claims 1 and 12 respectively.
As applied, Chen further discloses wherein the one or more processors, individually or in combination, are further configured to increase the program-verify levels in ascending order when programming memory cells (Fig. 21. See also para. 78; "A second programming operation (second pass) of those cells into that state then occurs by using a threshold voltage verify level 64 that is higher than the first verify level 61 and positioned within the distribution 62.". Further see para 97; "the Vpgm level is increased 0.2V and the count value progresses by 1")
Regarding claims 5 and 16, Shibata and Chen as supported by Dong disclose the limitations of claims 1 and 12 respectively.
As applied, Shibata further discloses wherein the one or more processors, individually or in combination, are further configured to store entangled logical pages of data in the first and second sets of memory cells (Fig. 9. See also para. 127; "Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.").
Regarding claim 8, Shibata and Chen as supported by Dong disclose the limitations of claim 1.
As applied, Shibata further discloses wherein the one or more processors, individually or in combination, are further configured to: read the programmed memory cells; and apply a logical function to a result to infer a bit stored in the programmed memory cells (Fig. 10. See also para. 144; " When a read operation is performed, the logic circuit 18 determines read data based on read results". Further, see para. 282; "the logic circuit 18 determines the read data of the first page based on the definitions of the data shown in FIG. 10, and outputs the determined read data DAT to the memory controller 20".)
Regarding claim 10, Shibata and Chen as supported by Dong disclose the limitations of claim 1.
As applied, Dong (as support for Chen) further discloses wherein the one or more processors, individually or in combination, are further configured to calibrate read thresholds of the first and second sets of memory cells to different levels (pg. 2721, Sect. II(C), col. 2; "The results also suggest that, during the memory read operations, sensing reference voltages for even and odd cells should be configured differently in order to minimize sensing BERs in the presence of significant cell-to-cell interference".)
Regarding claim 11, Shibata and Chen as supported by Dong disclose the limitations of claim 1.
As applied, Shibata further discloses wherein the memory comprises a three- dimensional memory (Fig. 4).
Claims 6 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Shibata et al. (US 20190259458; "Shibata") in view of Chen et al. (US 20050276101; "Chen") as supported by Dong et al. ("Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC NAND Flash Memory"; "Dong") and further in view of Li et al. (US 20060221697; "Li").
Regarding claims 6 and 17, Shibata and Chen as supported by Dong disclose the limitations of claims 1 and 12 respectively.
Shibata and Chen as supported by Dong are silent about the use of a quick pass write operation.
However, Li teaches wherein the one or more processors, individually or in combination, are further configured to perform a quick pass write operation (para. 43; "the exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values")
to provide a lower voltage threshold for each successive programming pulse after a respective verify level is satisfied (para. 43; "After each programming pulse, the memory is verified at a first, lower verify value, followed by a second verify at a second higher level. The second level is used to lock out a selected cell from further programming. The first, lower verify level is used to change the programming phase.").
Shibata, Chen as supported by Dong as well as Li are from the same field of endeavor as applicant's invention directed to programing of multi-state non-volatile memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Li's well-known quick-pass-write techniques on the memory device of Shibata and Chen as supported by Dong. Doing so would tighten the final threshold voltage distributions of the first and second sets of cells and thereby improve programming accuracy and reliability. The results of the combination would have been predictable.
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Shibata et al. (US 20190259458; "Shibata") in view of Chen et al. (US 20050276101; "Chen") as supported by Dong et al. ("Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC NAND Flash Memory"; "Dong") and further in view of Alrod et al. (US 20080151617)
Regarding claims 9 and 19, notwithstanding the rejection for indefiniteness above, Shibata and Chen as supported by Dong disclose the limitations of claims 1 and 12 respectively.
Shibata and Chen as supported by Dong disclose muti-level / paired-cell memory that stores a non-integer number of bits and that applies different program-verify levels to the first and second sets of memory cells. The paired-cell architecture inherently produces logical pages that can exhibit different error characteristics. It is silent with respect to explicitly setting or adjusting those program verify levels in a manner that takes into account relative differences in decoding quality or correction capability among the logical pages (as interpreted under the BRI of the indefiniteness rejection above).
However, Alrod teaches wherein the one or more processors (Fig. 4, controller 32. See also para. 62; "Controller 32 also supports error correction"), individually or in combination,
are further configured to set the program-verify levels in the first and second sets of memory cells based on a determined soft bit efficiency value (Abstr. "To read one or more flash memory cells, the threshold voltage of each cell is compared to at least one integral reference voltage and to at least one fractional reference voltage. Based on the comparisons, a respective estimated probability measure of each bit of an original bit pattern of each cell is calculated. This provides a plurality of estimated probability measures. Based at least in part on at least two of the estimated probability measures, respective original bit patterns of the cells are estimated").
Shibata, Chen as supported by Dong as well as Alrod are from the same field of endeavor as applicant's invention directed to programing of multi-state non-volatile memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the relative decoding-quality information taught by Alrod when selecting or adjusting the different program-verify levels already taught by Chen. Doing so would optimize the reliability of the different logical pages that result from Shibata's paired-cell mapping. The combination involves the predictable use of a known reliability metric in the known process of setting program-verify levels for multi-level cells, and would have yielded the predictable result of verify levels that reflect differences in page decoding quality.
Conclusion
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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