Detailed Action
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. The Amendment filed on 03/04/2026 has been entered. Claims 1, 12, 19 and 20 have been amended. Claims 8-11 and 14-18 stand withdrawn from consideration. Claims 1-20 remain pending in the application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-2, 5-7, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LIUS (US 20180062105 A1).
Regarding claim 1, LIUS (e.g., Figs. 2 and 4; Fig. 4D is reproduced for reference) discloses a display device comprising:
a light emitting element including a first electrode, a light emitting layer, and a second electrode (OLED 240 including an anode 413, a light emitting layer 415, and a cathode 417);
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Annotated version of LIUS Fig. 5
a first transistor including a first source electrode, a first active area, a first drain electrode, and a first gate electrode (transistor 220 including a source electrode 453, an active area 409, a drain electrode 454, and a gate electrode G2);
a second transistor including a second source electrode, a second active area, a second drain electrode, and a second gate electrode (transistor 210 including a source electrode 452, an active area 404, a drain electrode 451, and a gate electrode G1); and
a third transistor including a third source electrode, a third active area, a third drain electrode, and a third gate electrode (transistor 230 including a source electrode 455, an active area 410, a drain electrode 458, and a gate electrode G3), wherein
the first source electrode (source electrode 453 of transistor 220) is connected to the first electrode (anode 413 of OLED 240),
the second source electrode (source electrode 452 of transistor 210) is connected to the first gate electrode (gate electrode G2 of transistor 220),
the third drain electrode (drain electrode 458 of transistor 230) is connected to the first source electrode (anode 413 of OLED 240),
the second gate electrode (gate electrode G1 of transistor 210) and the third gate electrode (gate electrode G3 of transistor 230) are defined by a same conductive line (conductive layer comprising gate electrodes G1 and G3) which is disposed directly on a same insulating film (insulating layer 405), and
the second active area (active area 404 of transistor 210) and the third active area (active area 410 of transistor 230) are disposed in different layers (layer 405 and layer 408).
Regarding claim 2, LIUS (e.g., Figs. 2 and 4; Fig. 4D is reproduced for reference) discloses the display device of claim 1, further comprising a gate line (gate line S1) connected to the second gate electrode (gate electrode G1) and the third gate electrode (gate electrode G3), wherein the gate line applies a first gate voltage to the second gate electrode and a second gate voltage to the third gate electrode (gate line S1 applies a gate voltage to gate electrode G1 and a gate voltage to the gate electrode G3).
Regarding claim 5, LIUS (e.g., Figs. 2 and 4; Fig. 4D is reproduced for reference) discloses the display device of claim 1, further comprising: a first conductive layer in which the second gate electrode and the third gate electrode are disposed (first conductive layer including gate electrode G1 and gate electrode G3); a first active layer (active layer 404) disposed below the first conductive layer (first conductive layer including gate electrode G1 and gate electrode G3); and a second active layer (active layer 410) disposed above the first conductive layer (first conductive layer including gate electrode G1 and gate electrode G3), wherein one of the second active area and the third active area is defined by a portion of the first active layer (active layer 404 comprising active area 404), and the other of the second active area and the third active area is defined by a portion of the second active layer (active layer 410 comprising active area 410).
Regarding claim 6, LIUS (e.g., Figs. 2 and 4; Fig. 4D is reproduced for reference) discloses the display device of claim 1, wherein one of the second transistor and the third transistor has a bottom gate structure (transistor 230 has a bottom gate electrode G3), and the other of the second transistor and the third transistor has a top gate structure (transistor 210 has a top gate electrode G1).
Regarding claim 7, LIUS (e.g., Figs. 2 and 4; Fig. 4D is reproduced for reference) discloses the display device of claim 1, wherein the second transistor (transistor 210) and the third transistor (transistor 230) are disposed to be spaced apart from each other in a plan view (e.g., Figs. 2 and 4).
Regarding claim 19, LIUS (e.g., Figs. 2 and 4; Fig. 4D is reproduced for reference) discloses an electronic device comprises a display device, the display device comprising:
a light emitting element including a first electrode, a light emitting layer, and a second electrode (OLED 240 including an anode 413, a light emitting layer 415, and a cathode 417);
a first transistor including a first source electrode, a first active area, a first drain electrode, and a first gate electrode (transistor 220 including a source electrode 453, an active area 409, a drain electrode 454, and a gate electrode G2);
a second transistor including a second source electrode, a second active area, a second drain electrode, and a second gate electrode (transistor 210 including a source electrode 452, an active area 404, a drain electrode 451, and a gate electrode G1); and
a third transistor including a third source electrode, a third active area, a third drain electrode, and a third gate electrode (transistor 230 including a source electrode 455, an active area 410, a drain electrode 458, and a gate electrode G3), wherein
the first source electrode (source electrode 453 of transistor 220) is connected to the first electrode (anode 413 of OLED 240),
the second source electrode (source electrode 452 of transistor 210) is connected to the first gate electrode (gate electrode G2 of transistor 220),
the third drain electrode (drain electrode 458 of transistor 230) is connected to the first source electrode (anode 413 of OLED 240),
the second gate electrode (gate electrode G1 of transistor 210) and the third gate electrode (gate electrode G3 of transistor 230) are defined by a same conductive line (conductive layer comprising gate electrodes G1 and G3) which is disposed directly on a same insulating film (insulating layer 405), and
the second active area (active area 404 of transistor 230) and the third active area (active area 410 of transistor 230) are disposed in different layers (layer 405 and layer 408).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 3, 12-13 and 20 are rejected under 35 U.S.C. 103 as unpatentable over LIUS (US 20180062105 A1) in view of JANG (US 20250221045 A1).
Regarding claim 3, LIUS (e.g., Figs. 2 and 4; Fig. 4D is reproduced for reference) discloses the display device of claim 2, wherein the second gate electrode (gate electrode G1) and the third gate electrode (gate electrode G3) connected to the same gate line (gate line S). As another reference, JANG (e.g., Fig. 3) disclosed a display device comprising a pixel circuit similar to that disclosed by LIUS, wherein the second gate electrode (gate electrode GE1) of the second transistor (transistor T1) and the third gate electrode (gate electrode GE2) of the third transistor (transistor T2) are connected to the same gate line (gate line SL), and wherein the same conductive line defining the second gate electrode (gate electrode GE1) and the third gate electrode (gate electrode of transistor GE2) is a portion of the gate line ([0118]). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from JANG to the display device of LIUS. The combination/motivation would be to simplify the design and fabrication of the pixel circuit of the display device.
Regarding claim 12, LIUS (e.g., Figs. 2 and 5; Fig. 5 is reproduced for reference) discloses a display device comprising:
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a substrate (substrate 501);
a first active layer (active layer 508) disposed on the substrate (substrate 501);
a first conductive layer (first conductive layer including gate electrode G1, gate electrode G2, and gate electrode G3) disposed on the first active layer (active layer 404);
a second active layer (active layer 507) disposed on the first conductive layer (first conductive layer including gate electrode G1 and gate electrode G3);
a second conductive layer (second conductive layer including source electrodes and drain electrodes 541/542, 543/545, and 546/547) disposed on the first conductive layer (first conductive layer including gate electrode G1 and gate electrode G3);
a light emitting element (OLED 240) disposed on the second conductive layer (second conductive layer including source electrodes and drain electrodes 541/542, 543/545, and 546/547);
a first transistor including a first source electrode, a first active area, a first drain electrode, and a first gate electrode (transistor 220 including a source electrode 543, an active area 508, a drain electrode 545, and a gate electrode G2);
a second transistor including a second source electrode, a second active area, a second drain electrode, and a second gate electrode (transistor 210 including a source electrode 541, an active area 507, a drain electrode 542, and a gate electrode G1); and
a third transistor including a third source electrode, a third active area, a third drain electrode, and a third gate electrode (transistor 230 including a source electrode 546, an active area 509, a drain electrode 547, and a gate electrode G3), wherein
the first gate electrode, the second gate electrode, and the third gate electrode are defined by portions of the first conductive layer (first conductive layer including the gate electrode G1, the gate electrode G2, and the gate electrode G3) which is disposed directly on a same insulating film (insulating layer 506), and
one of the second active area and the third active area is defined by a portion of the first active layer (active layer 507 comprising active area 507), and
the other of the second active area and the third active area is defined by a portion of the second active layer (active layer 509 comprising active area 509).
LIUS the second gate electrode G1 and the third gate electrode G3 are connected to the same gate line S, but does not disclose the second gate electrode and the third gate electrode are integrally formed with each other. However, JANG discloses a display device comprising a pixel circuit similar to that disclosed by LIUS, wherein the second gate electrode (gate electrode GE1) of the second transistor (transistor T1) and the third gate electrode (gate electrode GE2) of the third transistor (transistor T2) are connected to the same gate line (gate line SL), and wherein the second gate electrode and the third gate electrode are integrally formed with each other ([0118]). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from JANG to the display device of LIUS. The combination/motivation would be to simplify the design and fabrication of the pixel circuit of the display device.
Regarding claim 13, LIUS in view of JANG discloses the display device of claim 12, LIUS (e.g., Figs. 2 and 5; Fig. 5 is reproduced for reference) discloses wherein the second transistor (transistor 210) and the third transistor (transistor 230) are disposed to be spaced apart from each other in a plan view (e.g., Figs. 2 and 4).
Regarding claim 20, LIUS (e.g., Figs. 2 and 5; Fig. 5 is reproduced for reference) discloses an electronic device comprises a display device, the display device comprising:
a substrate (substrate 501);
a first active layer (active layer 508) disposed on the substrate (substrate 501);
a first conductive layer (first conductive layer including gate electrode G1, gate electrode G2, and gate electrode G3) disposed on the first active layer (active layer 508);
a second active layer (active layer 507) disposed on the first conductive layer (first conductive layer including gate electrode G1, gate electrode G2, and gate electrode G3);
a second conductive layer (second conductive layer including source electrodes and drain electrodes 541/542, 543/545, and 546/547) disposed on the first conductive layer (first conductive layer including gate electrode G1 and gate electrode G3);
a light emitting element (OLED 240) disposed on the second conductive layer (second conductive layer including source electrodes and drain electrodes 541/542, 543/545, and 546/547);
a first transistor including a first source electrode, a first active area, a first drain electrode, and a first gate electrode (transistor 220 including a source electrode 543, an active area 508, a drain electrode 545, and a gate electrode G2);
a second transistor including a second source electrode, a second active area, a second drain electrode, and a second gate electrode (transistor 210 including a source electrode 541, an active area 507, a drain electrode 542, and a gate electrode G1); and
a third transistor including a third source electrode, a third active area, a third drain electrode, and a third gate electrode (transistor 230 including a source electrode 546, an active area 509, a drain electrode 547, and a gate electrode G3), wherein
the first gate electrode, the second gate electrode, and the third gate electrode are defined by portions of the first conductive layer (first conductive layer including gate electrode G1, gate electrode G2, and gate electrode G3) which is disposed directly on a same insulating film (insulating layer 506), and
one of the second active area and the third active area is defined by a portion of the first active layer (active layer 507 comprising active area 507), and
the other of the second active area and the third active area is defined by a portion of the second active layer (active layer 509 comprising active area 509).
LIUS the second gate electrode G1 and the third gate electrode G3 are connected to the same gate line S, but does not disclose the second gate electrode and the third gate electrode are integrally formed with each other. However, JANG discloses a display device comprising a pixel circuit similar to that disclosed by LIUS, wherein the second gate electrode (gate electrode GE1) of the second transistor (transistor T1) and the third gate electrode (gate electrode GE2) of the third transistor (transistor T2) are connected to the same gate line (gate line SL), and wherein the second gate electrode and the third gate electrode are integrally formed with each other ([0118]). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from JANG to the display device of LIUS. The combination/motivation would be to simplify the design and fabrication of the pixel circuit of the display device.
7. Claim 4 is rejected under 35 U.S.C. 103 as unpatentable over LIUS (US 20180062105 A1) in view of JANG (US 20250221045 A1) and further in view of Gupta (US 20240128274 A1).
Regarding claim 4, LIUS in view of JANG discloses the display device of claim 2, but does not disclose wherein the first gate voltage and the second gate voltage are applied to the gate line at different timings. LIUS (e.g., Figs. 2 and 4) discloses gate line S1 applies a gate voltage to the gate electrode G1 of the transistor 210 and a gate voltage to the gate electrode G3 of the transistor 230, and wherein the transistor 210 is a poly-silicon transistor and the transistor 230 is an oxide transistor. Gupta (e.g., Fig. 5) disclosed a display device comprising a pixel circuit similar to that disclosed by LIUS, wherein the transistor 30-1 is a PMOS poly-silicon transistor and the transistor 30-2 is a NMOS oxide transistor ([0050]-[0051] and [0058]). Therefore, the first gate voltage to turn on a PMOS poly-silicon transistor and the second gate voltage to turn on a NMOS oxide transistor are applied to the gate line at different timings. It would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from Gupta to the display device of LIUS in view of JANG. The combination/motivation would be to provide a provide a control signal to a pixel circuit with a hybrid oxide-silicon thin-film transistor structure.
Response to Arguments
8. Regarding claims 1, 12, and 19-20, applicant’s arguments have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. In view of amendments, the reference of LIUS (US 20180062105 A1; embodiment corresponding to Fig. 4D) has been used for new ground rejection of claims 1 and 19, and the reference of LIUS (US 20180062105 A1; embodiment corresponding to Fig. 5) and JANG (US 20250221045 A1) has been used for new ground rejection of claims 1 and 19
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623