Detailed Action
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/16/2026 has been entered.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-3, 5-7, 12-13, and 19-20 are rejected under 35 U.S.C. 103 as unpatentable over LIUS (US 20180062105 A1) in view of JANG (US 20250221045 A1).
Regarding claim 1, LIUS (e.g., Figs. 2 and 4; Fig. 4D is reproduced for reference) discloses a display device comprising:
a light emitting element including a first electrode, a light emitting layer, and a second electrode (OLED 240 including an anode 413, a light emitting layer 415, and a cathode 417);
PNG
media_image1.png
866
1436
media_image1.png
Greyscale
Annotated version of LIUS Fig. 4D
a first transistor including a first source electrode, a first active area, a first drain electrode, and a first gate electrode (transistor 220 including a source electrode 453, an active area 409, a drain electrode 454, and a gate electrode G2);
a second transistor including a second source electrode, a second active area, a second drain electrode, and a second gate electrode (transistor 210 including a source electrode 452, an active area 404, a drain electrode 451, and a gate electrode G1); and
a third transistor including a third source electrode, a third active area, a third drain electrode, and a third gate electrode (transistor 230 including a source electrode 455, an active area 410, a drain electrode 458, and a gate electrode G3), wherein
the first source electrode (source electrode 453 of transistor 220) is connected to the first electrode (anode 413 of OLED 240),
the second source electrode (source electrode 452 of transistor 210) is connected to the first gate electrode (gate electrode G2 of transistor 220),
the third drain electrode (drain electrode 458 of transistor 230) is connected to the first source electrode (anode 413 of OLED 240),
the second gate electrode (gate electrode G1 of transistor 210) and the third gate electrode (gate electrode G3 of transistor 230) are disposed directly on a same insulating film (insulating layer 405), and
the second active area (active area 404 of transistor 210) and the third active area (active area 410 of transistor 230) are disposed in different layers (layer 405 and layer 408).
LIUS does not disclose the second gate electrode and the third gate electrode are defined by a single continuous portion of a same conductive line. However, JANG (e.g., Figs. 3 and 6-10) discloses a display device comprising a pixel circuit (Figs. 3 and 8) similar to that disclosed by LIUS, comprising: a first transistor (transistor DT), a second transistor (transistor T1), and a third transistor (transistor T2), wherein the second gate electrode (gate electrode GE1) of the second transistor (transistor T1) and the third gate electrode (gate electrode GE2) of the third transistor (transistor T2) are defined by a single continuous portion of a same conductive line (Figs. 6 and 9 and [0118]; gate electrode GE1 and gate electrode GE2 are defined by a single continuous portion of a same conductive line SL). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from JANG to the display device of LIUS. The combination/motivation would be to simplify the design and fabrication of a pixel circuit including a plurality of transistors of a display device.
Regarding claim 2, LIUS in view of JANG discloses the display device of claim 1, LIUS (e.g., Figs. 2 and 4; Fig. 4D is reproduced for reference) discloses the display device further comprising a gate line (gate line S1) connected to the second gate electrode (gate electrode G1) and the third gate electrode (gate electrode G3), wherein the gate line applies a first gate voltage to the second gate electrode and a second gate voltage to the third gate electrode (gate line S1 applies a gate voltage to gate electrode G1 and a gate voltage to the gate electrode G3).
Regarding claim 3, LIUS in view of JANG discloses the display device of claim 1, JANG (e.g., Figs. 3 and 6-10) discloses wherein the same conductive line defining the second gate electrode and the third gate electrode is a portion of the gate line (Figs. 6 and 9 and [0118]; gate electrode GE1 and gate electrode GE2 are defined by a single portion of a same gate line SL). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from JANG to the display device of LIUS for the same reason above.
Regarding claim 5, LIUS in view of JANG discloses the display device of claim 1, LIUS (e.g., Figs. 2 and 4; Fig. 4D is reproduced for reference) discloses the display device further comprising: a first conductive layer in which the second gate electrode and the third gate electrode are disposed (first conductive layer including gate electrode G1 and gate electrode G3); a first active layer (active layer 404) disposed below the first conductive layer (first conductive layer including gate electrode G1 and gate electrode G3); and a second active layer (active layer 410) disposed above the first conductive layer (first conductive layer including gate electrode G1 and gate electrode G3), wherein one of the second active area and the third active area is defined by a portion of the first active layer (active layer 404 comprising active area 404), and the other of the second active area and the third active area is defined by a portion of the second active layer (active layer 410 comprising active area 410).
Regarding claim 6, LIUS in view of JANG discloses the display device of claim 1, LIUS (e.g., Figs. 2 and 4; Fig. 4D is reproduced for reference) discloses the display device wherein one of the second transistor and the third transistor has a bottom gate structure (transistor 230 has a bottom gate electrode G3), and the other of the second transistor and the third transistor has a top gate structure (transistor 210 has a top gate electrode G1).
Regarding claim 7, LIUS in view of JANG discloses the display device of claim 1, LIUS (e.g., Figs. 2 and 4; Fig. 4D is reproduced for reference) discloses the display device wherein the second transistor (transistor 210) and the third transistor (transistor 230) are disposed to be spaced apart from each other in a plan view (e.g., Figs. 2 and 4).
Regarding claim 12, LIUS (e.g., Figs. 2 and 5; Fig. 5 is reproduced for reference) discloses a display device comprising:
PNG
media_image2.png
790
1358
media_image2.png
Greyscale
a substrate (substrate 501);
a first active layer (active layer 508) disposed on the substrate (substrate 501);
a first conductive layer (first conductive layer including gate electrode G1, gate electrode G2, and gate electrode G3) disposed on the first active layer (active layer 404);
a second active layer (active layer 507) disposed on the first conductive layer (first conductive layer including gate electrode G1 and gate electrode G3);
a second conductive layer (second conductive layer including source electrodes and drain electrodes 541/542, 543/545, and 546/547) disposed on the first conductive layer (first conductive layer including gate electrode G1 and gate electrode G3);
a light emitting element (OLED 240) disposed on the second conductive layer (second conductive layer including source electrodes and drain electrodes 541/542, 543/545, and 546/547);
a first transistor including a first source electrode, a first active area, a first drain electrode, and a first gate electrode (transistor 220 including a source electrode 543, an active area 508, a drain electrode 545, and a gate electrode G2);
a second transistor including a second source electrode, a second active area, a second drain electrode, and a second gate electrode (transistor 210 including a source electrode 541, an active area 507, a drain electrode 542, and a gate electrode G1); and
a third transistor including a third source electrode, a third active area, a third drain electrode, and a third gate electrode (transistor 230 including a source electrode 546, an active area 509, a drain electrode 547, and a gate electrode G3), wherein
the first gate electrode, the second gate electrode, and the third gate electrode are defined by portions of the first conductive layer (first conductive layer including the gate electrode G1, the gate electrode G2, and the gate electrode G3) which is disposed directly on a same insulating film (insulating layer 506), and
one of the second active area and the third active area is defined by a portion of the first active layer (active layer 507 comprising active area 507), and
the other of the second active area and the third active area is defined by a portion of the second active layer (active layer 509 comprising active area 509).
LIUS does not disclose the second gate electrode and the third gate electrode are defined by a single continuous portion of the first conductive laver. However, JANG (e.g., Figs. 3 and 6-10) discloses a display device comprising a pixel circuit (Figs. 3 and 8) similar to that disclosed by LIUS, comprising: a first transistor (transistor DT), a second transistor (transistor T1), and a third transistor (transistor T2), wherein the second gate electrode (gate electrode GE1) of the second transistor (transistor T1) and the third gate electrode (gate electrode GE2) of the third transistor (transistor T2) are defined by a single continuous portion of the first conductive laver (Figs. 6 and 9 and [0118]; gate electrode GE1 and gate electrode GE2 are defined by a single continuous portion of a same conductive layer SL). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from JANG to the display device of LIUS. The combination/motivation would be to simplify the design and fabrication of a pixel circuit including a plurality of transistors of a display device.
Regarding claim 13, LIUS in view of JANG discloses the display device of claim 12, LIUS (e.g., Figs. 2 and 5; Fig. 5 is reproduced for reference) discloses wherein the second transistor (transistor 210) and the third transistor (transistor 230) are disposed to be spaced apart from each other in a plan view (e.g., Figs. 2 and 4).
Regarding claim 19, LIUS (e.g., Figs. 2 and 4; Fig. 4D is reproduced for reference) discloses an electronic device comprises a display device, the display device comprising:
a light emitting element including a first electrode, a light emitting layer, and a second electrode (OLED 240 including an anode 413, a light emitting layer 415, and a cathode 417);
a first transistor including a first source electrode, a first active area, a first drain electrode, and a first gate electrode (transistor 220 including a source electrode 453, an active area 409, a drain electrode 454, and a gate electrode G2);
a second transistor including a second source electrode, a second active area, a second drain electrode, and a second gate electrode (transistor 210 including a source electrode 452, an active area 404, a drain electrode 451, and a gate electrode G1); and
a third transistor including a third source electrode, a third active area, a third drain electrode, and a third gate electrode (transistor 230 including a source electrode 455, an active area 410, a drain electrode 458, and a gate electrode G3), wherein
the first source electrode (source electrode 453 of transistor 220) is connected to the first electrode (anode 413 of OLED 240),
the second source electrode (source electrode 452 of transistor 210) is connected to the first gate electrode (gate electrode G2 of transistor 220),
the third drain electrode (drain electrode 458 of transistor 230) is connected to the first source electrode (anode 413 of OLED 240),
the second gate electrode (gate electrode G1 of transistor 210) and the third gate electrode (gate electrode G3 of transistor 230) are disposed directly on a same insulating film (insulating layer 405), and
the second active area (active area 404 of transistor 230) and the third active area (active area 410 of transistor 230) are disposed in different layers (layer 405 and layer 408).
LIUS does not disclose the second gate electrode and the third gate electrode are defined by a single continuous portion of a same conductive line. However, JANG (e.g., Figs. 3 and 6-10) discloses a display device comprising a pixel circuit (Figs. 3 and 8) similar to that disclosed by LIUS, comprising: a first transistor (transistor DT), a second transistor (transistor T1), and a third transistor (transistor T2), wherein the second gate electrode (gate electrode GE1) of the second transistor (transistor T1) and the third gate electrode (gate electrode GE2) of the third transistor (transistor T2) are defined by a single continuous portion of a same conductive line (Figs. 6 and 9 and [0118]; gate electrode GE1 and gate electrode GE2 are defined by a single continuous portion of a same conductive line SL). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from JANG to the display device of LIUS. The combination/motivation would be to simplify the design and fabrication of a pixel circuit including a plurality of transistors of a display device.
Regarding claim 20, LIUS (e.g., Figs. 2 and 5; Fig. 5 is reproduced for reference) discloses an electronic device comprises a display device, the display device comprising:
a substrate (substrate 501);
a first active layer (active layer 508) disposed on the substrate (substrate 501);
a first conductive layer (first conductive layer including gate electrode G1, gate electrode G2, and gate electrode G3) disposed on the first active layer (active layer 508);
a second active layer (active layer 507) disposed on the first conductive layer (first conductive layer including gate electrode G1, gate electrode G2, and gate electrode G3);
a second conductive layer (second conductive layer including source electrodes and drain electrodes 541/542, 543/545, and 546/547) disposed on the first conductive layer (first conductive layer including gate electrode G1 and gate electrode G3);
a light emitting element (OLED 240) disposed on the second conductive layer (second conductive layer including source electrodes and drain electrodes 541/542, 543/545, and 546/547);
a first transistor including a first source electrode, a first active area, a first drain electrode, and a first gate electrode (transistor 220 including a source electrode 543, an active area 508, a drain electrode 545, and a gate electrode G2);
a second transistor including a second source electrode, a second active area, a second drain electrode, and a second gate electrode (transistor 210 including a source electrode 541, an active area 507, a drain electrode 542, and a gate electrode G1); and
a third transistor including a third source electrode, a third active area, a third drain electrode, and a third gate electrode (transistor 230 including a source electrode 546, an active area 509, a drain electrode 547, and a gate electrode G3), wherein
the first gate electrode, the second gate electrode, and the third gate electrode are defined by portions of the first conductive layer (first conductive layer including gate electrode G1, gate electrode G2, and gate electrode G3) which is disposed directly on a same insulating film (insulating layer 506), and
one of the second active area and the third active area is defined by a portion of the first active layer (active layer 507 comprising active area 507), and
the other of the second active area and the third active area is defined by a portion of the second active layer (active layer 509 comprising active area 509).
LIUS does not disclose the second gate electrode and the third gate electrode are defined by a single continuous portion of the first conductive layer. However, JANG (e.g., Figs. 3 and 6-10) discloses a display device comprising a pixel circuit (Figs. 3 and 8) similar to that disclosed by LIUS, comprising: a first transistor (transistor DT), a second transistor (transistor T1), and a third transistor (transistor T2), wherein the second gate electrode (gate electrode GE1) of the second transistor (transistor T1) and the third gate electrode (gate electrode GE2) of the third transistor (transistor T2) are defined by a single continuous portion of the first conductive laver (Figs. 6 and 9 and [0118]; gate electrode GE1 and gate electrode GE2 are defined by a single continuous portion of a same conductive layer SL). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from JANG to the display device of LIUS. The combination/motivation would be to simplify the design and fabrication of a pixel circuit including a plurality of transistors of a display device.
5. Claim 4 is rejected under 35 U.S.C. 103 as unpatentable over LIUS (US 20180062105 A1) in view of JANG (US 20250221045 A1) and further in view of Gupta (US 20240128274 A1).
Regarding claim 4, LIUS in view of JANG discloses the display device of claim 2, but does not disclose wherein the first gate voltage and the second gate voltage are applied to the gate line at different timings. LIUS (e.g., Figs. 2 and 4) discloses gate line S1 applies a gate voltage to the gate electrode G1 of the transistor 210 and a gate voltage to the gate electrode G3 of the transistor 230, and wherein the transistor 210 is a poly-silicon transistor and the transistor 230 is an oxide transistor. Gupta (e.g., Fig. 5) disclosed a display device comprising a pixel circuit similar to that disclosed by LIUS, wherein the transistor 30-1 is a PMOS poly-silicon transistor and the transistor 30-2 is a NMOS oxide transistor ([0050]-[0051] and [0058]). Therefore, the first gate voltage to turn on a PMOS poly-silicon transistor and the second gate voltage to turn on a NMOS oxide transistor are applied to the gate line at different timings. It would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from Gupta to the display device of LIUS in view of JANG. The combination/motivation would be to provide a provide a control signal to a pixel circuit with a hybrid oxide-silicon thin-film transistor structure.
Response to Arguments
6. Applicant's arguments filed 06/16/2026 have been fully considered but they are not persuasive.
10. Applicant has amended claims 1, 12, and 19-20. Applicant further argues that the cited references do not disclose the new limitations “the second gate electrode and the third gate electrode are defined by a single continuous portion of a same conductive line” recited in claim 1 and similarly recited in claims 12 and 19-20.
The examiner respectfully disagrees with applicant’s arguments. JANG (e.g., Figs. 3 and 6-10; Fig. 6 is reproduced below for reference) discloses a display device comprising a pixel circuit (Figs. 3 and 8) similar to that disclosed by LIUS (Fig. 2), comprising: a first transistor DT, a second transistor T1, and a third transistor T2, wherein the second gate electrode GE1 of the second transistor T1 and the third gate electrode GE2 of the third transistor T2 are defined by a single continuous portion of a same conductive layer SL (Figs. 6 and 9 and [0118]).
PNG
media_image3.png
200
360
media_image3.png
Greyscale
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (FP 7.96)
SON (US 20230071094 A1) discloses a display device.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YUZHEN SHEN/Primary Examiner, Art Unit 2623
Prosecution Insights