DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed January 29, 2025 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered. The examiner notes that NPL document 6 has not been submitted and is therefore lined through. The examiner notes that NPL documents 1 – 5 are contained in the file wrappers of parent U.S. Application No. 18/050,080 and 16/794,787 and are therefore considered.
Specification
The Objection to the instant Specification for the title of the invention not being descriptive is withdrawn in light of the amendment to the instant Specification.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 – 5, 7 – 13, and 15 – 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 4, 7 – 8, and 10 - 11 of U.S. Patent No. 12,223,926. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Claim
Instant Application (19/040,153)
Claim
U.S. Patent No. 12,223,926 B2
Differences/Similarities explained
1
A display device comprising:
1
A display device comprising:
None
a plurality of pixels connected to a plurality of data lines; a data driving circuit configured to output a plurality of data voltages to the plurality of data lines in response to a main clock signal and a clock signal; and
a display panel comprising a plurality of data lines, a plurality of gate lines and a plurality of pixels; a data driving circuit configured to output a plurality of data voltages to the plurality of data lines in response to a data control signal; a gate driving circuit configured to output a plurality of gate signals to the plurality of gate lines in response to a gate control signal; and
Obvious to go broader
a timing controller configured to output a plurality of image signals, the main clock signal, a delay signal, and the clock signal,
a timing controller configured to output the data control signal and the gate control signal, wherein the data control signal includes a main clock signal and a clock signal,
Obvious to go broader
wherein the data driving circuit comprises:
wherein the data driving circuit comprising a plurality of data integrated circuits, each of the plurality of data integrated circuits comprises:
Obvious to go broader
a shift register configured to output a plurality of latch clock signals that are sequentially activated in response to the clock signal;
a shift register configured to receive the clock signal from the timing controller and output a plurality of latch clock signals that are sequentially activated in response to the clock signal;
Obvious to go broader
a latch circuit configured to latch the plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals;
a latch circuit configured to latch a plurality of image signals from the timing controller in response to the plurality of latch clock signals from the shift register and output a plurality of digital image signals in response to a plurality of latch output signals;
Obvious to go broader
an output circuit configured to convert the plurality of digital image signals to the plurality of data voltages; and
an output circuit configured to convert the plurality of digital image signals to the plurality of data voltages; and
none
a clock generator configured to receive the main clock signal and the delay signal, divide the main clock signal to generate the plurality of latch output signals, and output a first latch output signal and a second latch output signal among the plurality of latch output signals, wherein the clock generator adjusts a phase difference between the plurality of latch output signals in response to the display signal,
a clock generator configured to receive the main clock signal, divide the main clock signal to generate the plurality of latch output signals and output the plurality of latch output signals,
Similar in Scope
8
wherein the timing controller further outputs a delay signal and the clock generator adjusts a phase difference between the plurality of latch output signals in response to the delay signal
Similar in Scope
wherein the latch circuit comprises:
wherein the latch circuit comprises:
none
a first latch group configured to latch a first subset of the plurality of image signals based on a first subset of the latch clock signals and output a plurality of first digital image signals of the plurality of digital image signals in response to the first latch output signal during a first period; and
a first latch group configured to receive a first subset of the image signals, a first subset of the latch clock signals and a first latch output signal from among the plurality of latch output signals, latch the first subset of the image signals based on the first subset of the latch clock signals and output a plurality of first digital image signals of the plurality of digital image signals in response to the first latch output signal; and
Obvious to go broader
a second latch group configured to latch a second subset of the plurality of image signals based on a second subset of the latch clock signals and output a plurality of second digital image signals of the plurality of digital image signals in response to the second latch output signal during a second period, and
a second latch group configured to receive a second subset of the image signals, a second subset of the latch clock signals and a second latch output signal from among the plurality of latch output signals, latch the second subset of the image signals based on the second subset of the latch clock signals and output a plurality of second digital image signals of the plurality of digital image signals in response to the second latch output signal among the plurality of latch output signals, and
Obvious to go broader
wherein the first period is not overlapped with the second period.
wherein an active portion of the first latch output signal is not overlapped with an active portion of the second latch output signal.
Obvious to go broader
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 7 of U.S. Patent No. 11,488,560. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Claim
Instant Application (19/040,153)
Claim
U.S. Patent No. 11,488,560 B2
Differences/Similarities explained
1
A display device comprising:
1
A display device comprising:
None
a plurality of pixels connected to a plurality of data lines; a data driving circuit configured to output a plurality of data voltages to the plurality of data lines in response to a main clock signal and a clock signal; and
a data driving circuit including a plurality of data integrated circuits outputting a plurality of data voltages comprising at least first and second data voltages based on the main clock signal; a gate driving circuit configured to output a plurality of gate signals; and a display panel comprising a plurality of data lines, a plurality of gate lines and a plurality of pixels, the display panel configured to receive the data voltages from the data driving circuit through the data lines and to receive the gate signals only from the gate driving circuit through the gate lines;
Obvious to go broader
a timing controller configured to output a plurality of image signals, the main clock signal and the clock signal,
a timing controller configured to output a plurality of digital image signals, a main clock signal, a clock signal separate from the main clock signal, an output control signal and a delay signal;
Obvious to go broader
wherein the data driving circuit comprises:
wherein each of the plurality of data integrated circuits comprises:
Obvious to go broader
a shift register configured to output a plurality of latch clock signals that are sequentially activated in response to the clock signal;
a shift register configured to receive the clock signal from the timing controller to output a plurality of latch clock signals that are sequentially activated in response to the clock signal;
Obvious to go broader
a latch circuit configured to latch the plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals;
a latch circuit configured to receive the first to third latch output signals from the clock generator and receive the plurality of digital image signals from the timing controller, and comprising a plurality of first latches, a plurality of second latches and a plurality of third latches configured to output the plurality of digital image signals in response to the first to third latch output signals; and
Obvious to go broader
an output circuit configured to convert the plurality of digital image signals to the plurality of data voltages; and
a clock generator configured to receive the main clock signal and the delay signal, divide the main clock signal to generate the plurality of latch output signals, and output a first latch output signal and a second latch output signal among the plurality of latch output signals, wherein the clock generator adjusts a phase difference between the plurality of latch output signals in response to the display signal,
a clock generator configured to receive the main clock signal, the output control signal and the delay signal from the timing controller, generate first to third latch output signals from the main clock signal based on the output control signal and the delay signal, and output the first to third latch output signals;
Similar in Scope
7
wherein the clock generator adjusts a phase difference between the first to third latch output signals in response to the delay signal
Similar in Scope
wherein the latch circuit comprises: a first latch group configured to latch a first subset of the plurality of image signals based on a first subset of the latch clock signals and output a plurality of first digital image signals of the plurality of digital image signals in response to the first latch output signal during a first period; and a second latch group configured to latch a second subset of the plurality of image signals based on a second subset of the latch clock signals and output a plurality of second digital image signals of the plurality of digital image signals in response to the second latch output signal during a second period, and
wherein each of the plurality of first latches, each of the plurality of second latches and each of the plurality of third latches latch one of the plurality of digital image signals in response to a corresponding one of the plurality of latch clock signals, wherein the plurality of first latches output first digital image signals of the digital image signals, the plurality of second latches output second digital image signals of the digital image signals, and the plurality of third latches output third digital image signals of the digital image signals, wherein the first latch output signal and the third latch output signal are activated during a first period, respectively and the second latch output signal is activated during a second period after the first period when the output control signal indicates a first direction, wherein the first latch output signal is activated during the first period, the second latch output signal is activated during the second period, and the third latch output signal is activated during a third period after the second period when the output control signal indicates a second direction, wherein each of the plurality of first latches output simultaneously a respective one of the first digital image signals in response to the first latch output signal, wherein each of the plurality of third latches output simultaneously a respective one of the third digital image signals in response to the third latch output signal, wherein each of the plurality of second latches output simultaneously a respective one of the second digital image signals in response to the second latch output signal, wherein the data lines comprise first data lines configured to receive the first digital image signals, second data lines configured to receive the second digital image signals, and third data lines configured to receive the third digital image signals, and wherein the second data lines are disposed between the first data lines and the third data lines,
Obvious to go broader
wherein the first period is not overlapped with the second period.
wherein the first and second periods do not overlap one another when the output control signal indicates the first direction and the first to third periods do not overlap one another when the output control signal indicates the second direction, wherein the clock generator receives the main clock signal in a data control signal that it receives directly from the timing controller, wherein the data control signal further includes the clock signal.
Obvious to go broader
wherein the first and second periods do not overlap one another when the output control signal indicates the first direction and the first to third periods do not overlap one another when the output control signal indicates the second direction, wherein the clock generator receives the main clock signal in a data control signal that it receives directly from the timing controller, wherein the data control signal further includes the clock signal.
Obvious to go broader
Allowable Subject Matter
Claims 18 – 20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Shimizu (U.S. PG Pub 2004/0189579) teach an electronic device comprising: a controller (Figure 2, Element not labeled, but is the external supply of the display data) configured to output a plurality of control signals (Element D); and a display module (Figure 2) configured to display an image in response to the plurality of control signals (Element D), wherein the display module (Figure 2) comprises: a plurality of pixels (Elements 11 - 13) connected to a plurality of data lines (Element 14); a timing controller (Element 4) configured to output a plurality of image signals (Elements DR, DG, and DB), a main clock signal (Element LS) and a clock signal (Element SP); and a data driving circuit (Element 2) configured to output a plurality of data voltages (Elements X1 - Z100) to the plurality of data lines (Element 14) in response to the plurality of image signals (Elements DR, DG, and DB. ), the main clock signal (Element LS) and the clock signal (Element SP); and wherein the data driving circuit (Element 2) comprises: a latch circuit (Elements 23 and 24) configured to latch the plurality of image signals (Elements DR, DG, and DB) in response to a plurality of latch clock signals (Element control signal) and output a plurality of digital image signals (Elements X1 - Z100) in response to a plurality of latch output signals (Element LS); an output circuit (Elements 26 - 27) configured to convert the plurality of digital image signals (Elements X1 - Z100) to the plurality of data voltages (Elements X1 - Z100); and a clock generator (Elements 34) configured to receive the main clock signal (Element LS) and output a first latch output signal (Element LS, Sub-Element not labeled but LS signal connected to X1, Y1, and Z1) and a second latch output signal (Element LS, Sub-Element not labeled but LS signal connected to X2, Y2, and Z2 after it has been delayed), wherein the latch circuit (Elements 23 and 24) comprises: a first latch group (Elements 33, Sub-Elements not labeled but are the latches connected to X1, Y1, and Z1) configured to latch a first subset of the plurality of image signals (Elements DR, DG, and DB) based on a first subset of the latch clock signals (Element control signal) and output a plurality of first digital image signals (Elements X1, Y1, and Z1) of the plurality of digital image signals (Elements X1 - Z100) in response to the first latch output signal (Element LS, Sub-Element not labeled but LS signal connected to X1, Y1, and Z1) during a first period (Element not labeled, but is when cells X1, Y1, Z1, X100, Y100, and Z100 are fed the LS signal); and a second latch group (Elements 33, Sub-Elements not labeled but are the latches connected to X2, Y2, and Z2) configured to latch a second subset of the plurality of image signals (Elements DR, DG, and DB) based on a second subset of the latch clock signals (Element control signal) and output a plurality of second digital image signals (Elements X2, Y2, and Z2) of the plurality of digital image signals (Elements X1 - Z100) in response to the second latch output signal (Element LS, Sub-Element not labeled but LS signal connected to X2, Y2, and Z2 after it has been delayed) during a second period (Element not labeled, but is when cells X2, Y2, and Z2 are fed the LS signal after the delay circuit), and wherein the first period (Element not labeled, but is when cells X1, Y1, Z1, X100, Y100, and Z100 are fed the LS signal) is not overlapped with (Seen in Figure 8) the second period (Element not labeled, but is when cells X2, Y2, and Z2 are fed the LS signal after the delay circuit).
Fukuo (U.S. PG Pub 2008/0068360) teach wherein the shift register (Figure 3, Element 151. Paragraph 32) includes a cascade of flip flops (Figure 3, Elements F1 – F7. Paragraph 32) sharing the clock signal (Figure 3, Element CLK. Paragraph 32) in which an output of each of the flip flops (Figure 3, Elements F1 – F7. Paragraph 32) is connected to (Seen in Figure 3) a data input of a next one of the flip flops (Figure 3, Elements F1 – F7. Paragraph 32) in the cascade.
However, the prior art of record fails to teach at least “a clock generator configured to receive the main clock signal and the delay signal, divide the main clock signal to generate the plurality of latch output signals. and output a first latch output signal and a second latch output signal among the plurality of latch output signals, wherein the clock generator adjusts a phase difference between the plurality of latch output signals in response to the delay signal, wherein the latch circuit comprises: a first latch group configured to latch a first subset of the plurality of image signals based on a first subset of the latch clock signals and output a plurality of first digital image signals of the plurality of digital image signals in response to the first latch output signal during a first period within one horizontal period; and a second latch group configured to latch a second subset of the plurality of image signals based on a second subset of the latch clock signals and output a plurality of second digital image signals of the plurality of digital image signals in response to the second latch output signal during a second period within the one horizontal period, and wherein the first period is not overlapped with the second period” in combination with the other limitations of at least Claim 18.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.B.S/Examiner, Art Unit 2625
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625