DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 12,249,381. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1=20 would have been obvious over claims 1-8 of the patent..
Regarding claims 1-4, claims 1-4 of the patent recites a memory device comprising:
a memory array comprising memory cells associated with a plurality of wordlines; and
control logic coupled with the memory array, the control logic to perform operations comprising:
determining a metadata value characterizing a first read level voltage of a first threshold voltage distribution (a highest threshold voltage distribution) of a subset of the memory cells;
adjusting, based on the metadata value, a second read level voltage for a second threshold voltage distribution (a second highest threshold distribution) of the subset of the memory cells; and
causing, to perform an initial calibrated read of the subset of the memory cells, the adjusted second read level voltage to be applied to a wordline of the plurality of wordlines to read the second threshold voltage distribution.
It would have been obvious to one having ordinary skill in the art to recognize that the memory device of claims 1-4 of the instant application and the memory device of claims 1-4 of the patent are identical in structure; therefore, the differences between two sets of claims are only a functional limitation.
Regarding claim 5, claim 5 of the patent recites the memory device of claim 1, wherein the operations further comprise:
performing a dual-strobe sensing operation associated with the first read level voltage to sense at a target read level voltage and at a low read level voltage that is lower than the target read level voltage for the first threshold voltage distribution; and
storing, in a primary data cache, the target read level voltage and the low read level voltage.
Regarding claim 6, claim 6 of the patent recites the memory device of claim 5, wherein the operations further comprise:
determining, based on a charge loss characteristic of the first threshold voltage distribution, that a charge loss of the subset of the memory cells does not satisfy a threshold voltage drop criterion; and
storing, in a secondary data cache, the target read level voltage with a second sensed read voltage value for the second threshold voltage distribution.
Regarding claim 7, claim 7 of the patent recites the memory device of claim 1, wherein adjusting the second read level voltage comprises:
identifying, in a lookup table, an entry mapping the metadata value to a corresponding read voltage offset; and
applying the corresponding read voltage offset to the second read level voltage.
Regarding claim 8, claims 8 and 1 of the patent recites the memory device of claim 1, wherein the subset of the memory cells is a memory page, and wherein the metadata value comprises at least one of a failed byte count or a failed bit count.
Regarding claim 9, claims 1, 2, 3, 5 and 6 of the patent recites a memory device comprising:
a memory array comprising memory cells associated with a plurality of wordlines; and
control logic coupled with the memory array, the control logic to perform operations comprising:
causing a dual-strobe sensing operation to be performed for a first read level voltage, of a first threshold voltage distribution of a subset of the memory cells, comprising sensing at a target read level voltage and determining a measured value characterizing the first read level voltage; and
in response to determining that a charge loss associated with the first threshold voltage distribution satisfies a threshold voltage drop criterion:
adjusting, based on the measured value, the first read level voltage;
causing, to perform an initial calibrated read operation of the subset of the memory cells, the adjusted first read level voltage to be applied to a wordline of the memory array to read the first threshold voltage distribution; and
causing calibrated read operations to be performed of one or more additional threshold voltage distributions (claim 2 and 3 of the patent) of the subset of the memory cells using an adjusted read level voltage, which is based on the measured value, for each respective additional threshold voltage distribution.
It would have been obvious to one having ordinary skill in the art to recognize that the memory device of claims 9-14 and the memory device of claims 1-8 are identical in structure; therefore, the differences between two sets of claims are only functional limitations.
Regarding 15, claims 1, 2, 5 and 6 of the patent recite a memory device comprising:
a memory array comprising memory cells associated with a plurality of wordlines; and
control logic coupled with the memory array, the control logic to perform operations comprising:
causing a dual-strobe sensing operation to be performed for a first read level voltage, of a first threshold voltage distribution of a subset of the memory cells, comprising sensing at a target read level voltage and determining a measured value characterizing the first read level voltage; and
in response to determining that a charge loss associated with the first threshold voltage distribution satisfies a threshold voltage drop criterion:
adjusting, based on the measured value, the first read level voltage;
causing, to perform an initial calibrated read operation of the subset of the memory cells, the adjusted first read level voltage to be
applied to a wordline of the memory array to read the first threshold voltage distribution;
adjusting, based on the measured value, a second read level voltage for a second threshold voltage distribution of the subset of memory cells; and
causing, to perform a second calibrated read operation of the subset of memory cells, the adjusted second read level voltage to be applied to the wordline to read the second threshold voltage distribution.
It would have been obvious to one having ordinary skill in the art to recognize that the memory device of claims 15-20 and the memory device of claims 1-8 are identical in structure; therefore, the differences between two sets of claims are only functional limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUAN HOANG/ Primary Examiner, Art Unit 2827
Prosecution Insights