CTNF 19/040,550 CTNF 99282 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1, 3-4, 11, 14 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash et al. (US 2022/0284971), hereinafter Prakash, in view of Kathawala et al. (US 2017/0148525), hereinafter Kathawala . Regarding claim 1 , Prakash teaches a method of operating a memory device which includes a memory circuit ( Prakash, Fig. 1A ) , the method comprising: receiving a program command, an address, and data from a controller ( Prakash, para. [0046], lines 1-2, “Each memory cell may be associated with a data state according to write data in a program command”; para. [0084], lines 16-20, “If the host provides a logical address to which data is to be read/written, the flash memory controller can convert the logical address received from the host to a physical address in the flash memory. [Alternatively, the host can provide the physical address]” ) ; and performing a program operation on a selected word line corresponding to the address according to the program command to store the data ( Prakash, Abstract teaches performing programming operations on selected word lines and subsequently performing verify operations on the programmed memory cells ) , wherein the program operation comprises: applying a first program voltage to the selected word line ( Prakash, Abstract, lines 12-15, “The verify voltage level is applied to the one of the plurality of word lines selected for programming following an application of a program voltage during a program operation” ) ; applying a first verify voltage and a second verify voltage to the selected word line based on device information stored in the memory circuit ( Prakash, Abstract, lines 7-12, “A control circuit is coupled to the plurality of word lines and is configured to detect at least one use characteristic of the memory apparatus. The control circuit adjusts a verify voltage level by one of a plurality of verify level offsets based on the at least one use characteristic that is detected. The verify voltage level is applied to the one of the plurality of word lines selected for programming following an application of a program voltage during a program operation” ) ; and detecting an error status of the device information stored in the memory circuit, based on a level difference of the first verify voltage and the second verify voltage. Prakash fails to teach detecting an error status of the device information stored in the memory circuit, based on a level difference of the first verify voltage and the second verify voltage. However, Kathawala, in an analogous art, teaches detecting an error status of the device information stored in the memory circuit, based on a level difference of the first verify voltage and the second verify voltage ( Kathawala, Fig. 6C; first and second threshold sets equate to first and second verify voltages, first and second error parameters equate to information derived from first and second verify conditions, and comparing the first and second parameter sets equates to determining a status based on a level difference ) . Prakash and Kathawala are both considered to be analogous to the claimed invention because both are in the same field of utilizing verify voltage information in memory apparatuses/devices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Prakash to incorporate the teachings of Kathawala by including the functionality of integrity determination using multiple verify voltage conditions. The suggestion/motivation for doing so would be to improve the reliability of verify voltage determination and program operations. Regarding claim 3 , the combination of Prakash in view of Kathawala teaches the method of claim 1, wherein the device information includes information about a first default level and a first offset level corresponding to the first verify voltage, and information about a second default level and a second off set level corresponding to the second verify voltage, and wherein the method further comprises generating the first verify voltage based on the information about the first default level and the first off set level, and generating the second verify voltage based on the information about the second default level and the second offset level ( Prakash, Fig. 16, block 1202 ) . Regarding claim 4 , the combination of Prakash in view of Kathawala teaches the method of claim 1, wherein the applying of the first verify voltage and the second verify voltage to the selected word line ( Prakash, Abstract, lines 7-12, “A control circuit is coupled to the plurality of word lines and is configured to detect at least one use characteristic of the memory apparatus. The control circuit adjusts a verify voltage level by one of a plurality of verify level offsets based on the at least one use characteristic that is detected. The verify voltage level is applied to the one of the plurality of word lines selected for programming following an application of a program voltage during a program operation” ) and the detecting of error status of the device information stored in the memory circuit based on the level difference are performed in parallel ( Kathawala, Fig. 6C teaches determining first and second error parameters from first and second threshold conditions, comparing the parameters, and generating a determination result ) . The references do not explicitly teach the verify voltage operations and error status detection being performed in parallel, however a person of ordinary skill in the art would understand that the comparison operation taught in Kathawala may be performed concurrently with verify processing instead of waiting for all of the verification operations to be completed. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Prakash to incorporate the teachings of Kathawala by including the functionality of verify voltage processing and error detection to occur in parallel. The suggestion/motivation for doing so would be to reduce processing latency and improving the efficiency of programming operations. Regarding claim 11 , Prakash teaches a memory device comprising: a memory circuit configured to store device information ( Prakash, Fig. 1A ) ; a memory cell array comprising a plurality of memory cells connected to a plurality of word lines ( Prakash, Figs. 1A, 7A, 7B, 8A & 8B ) ; a control logic circuit configured to generate a first verify code and a second verify code, based on the device information, during a program verify operation ( Prakash, para. [0008], lines 10-16, “The control circuit is also configured to adjust a verify voltage by one of a plurality of verify level offsets based on the at least one use characteristic of the memory apparatus detected. The verify voltage is applied to the one of the plurality of word lines selected for programming following an application of a program voltage during a program operation” ) ; a voltage generating circuit configured to generate a first verify voltage based on the first verify code and generate a second verify voltage based on the second verify code, during the program verify operation ( Prakash, Fig. 1C, voltage level generation circuit 135 ) ; and a row address decoder configured to apply the first verify voltage and the second verify voltage to a selected word line among the plurality of word lines, during the program verify operation ( Prakash, Fig. 7B, row decoder 799 ) . Prakash fails to teach an error checker circuit configured to detect an error status of the device information, based on a level difference of the first verify code and the second verify code, during the program verify operation. However, Kathawala, in an analogous art, teaches detecting an error status of the device information stored in the memory circuit, based on a level difference of the first verify voltage and the second verify voltage ( Kathawala, Fig. 2, verify voltage adjust module 218 ) . Prakash and Kathawala are both considered to be analogous to the claimed invention because both are in the same field of utilizing verify voltage information in memory apparatuses/devices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Prakash to incorporate the teachings of Kathawala by including the functionality of integrity determination using multiple verify voltage conditions. The suggestion/motivation for doing so would be to improve the reliability of verify voltage determination and program operations. Regarding claim 14 , the combination of Prakash in view of Kathawala teaches the memory device of claim 11, further comprising a pass/fail checker circuit configured to determine a pass state of a program operation, based on a first cell counting value and a second cell counting value ( Kathawala, Fig. 6C; first and second threshold sets equate to first and second verify voltages, first and second error parameters equate to information derived from first and second verify conditions, and comparing the first and second parameter sets equates to determining a status based on a level difference ) , wherein the first cell counting value is obtained by counting first memory cells, which are determined based on the first verify voltage, from among memory cells connected to the selected word line, and wherein the second cell counting value is obtained by counting second memory cells, which are determined based on the second verify voltage, from among the memory cells connected to the selected word line ( Prakash, Abstract, lines 7-12, “A control circuit is coupled to the plurality of word lines and is configured to detect at least one use characteristic of the memory apparatus. The control circuit adjusts a verify voltage level by one of a plurality of verify level offsets based on the at least one use characteristic that is detected. The verify voltage level is applied to the one of the plurality of word lines selected for programming following an application of a program voltage during a program operation” ) . It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Prakash to incorporate the teachings of Kathawala by including the functionality of integrity determination using multiple verify voltage conditions. The suggestion/motivation for doing so would be to improve the reliability of verify voltage determination and program operations. Regarding claim 16 , Prakash teaches a method of operating a memory device which includes a memory circuit ( Prakash, Fig. 1A ) , the method comprising: receiving a program command, an address, and data from a controller ( Prakash, para. [0046], lines 1-2, “Each memory cell may be associated with a data state according to write data in a program command”; para. [0084], lines 16-20, “If the host provides a logical address to which data is to be read/written, the flash memory controller can convert the logical address received from the host to a physical address in the flash memory. [Alternatively, the host can provide the physical address]” ) ; and sequentially performing a plurality of program loops on a selected word line corresponding to the address to perform a program operation of storing the data ( Prakash, Abstract teaches performing programming operations on selected word lines and subsequently performing verify operations on the programmed memory cells ) , according to the program command, wherein each of the plurality of program loops comprises: applying a program voltage to the selected word line to control threshold voltages of selected memory cells connected to the selected word line ( Prakash, Abstract, lines 12-15, “The verify voltage level is applied to the one of the plurality of word lines selected for programming following an application of a program voltage during a program operation” ) ; and applying verify voltages to the selected word line to verify a program state of the selected memory cells ( Prakash, Abstract, lines 7-12, “A control circuit is coupled to the plurality of word lines and is configured to detect at least one use characteristic of the memory apparatus. The control circuit adjusts a verify voltage level by one of a plurality of verify level offsets based on the at least one use characteristic that is detected. The verify voltage level is applied to the one of the plurality of word lines selected for programming following an application of a program voltage during a program operation” ) . Prakash fails to teach detecting an error status of device information stored in the memory circuit, based on a level difference of the verify voltages. However, Kathawala, in an analogous art, teaches detecting an error status of device information stored in the memory circuit, based on a level difference of the verify voltages ( Kathawala, Fig. 6C; first and second threshold sets equate to first and second verify voltages, first and second error parameters equate to information derived from first and second verify conditions, and comparing the first and second parameter sets equates to determining a status based on a level difference ) . Prakash and Kathawala are both considered to be analogous to the claimed invention because both are in the same field of utilizing verify voltage information in memory apparatuses/devices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Prakash to incorporate the teachings of Kathawala by including the functionality of integrity determination using multiple verify voltage conditions. The suggestion/motivation for doing so would be to improve the reliability of verify voltage determination and program operations. Regarding claim 17 , the combination of Prakash in view of Kathawala teaches the method of claim 16, wherein the device information includes information about a default level and information about an offset level, for each of the verify voltages, and wherein the method further comprises generating the verify voltages based on the information about the default level and the information about the offset level. ( Prakash, Fig. 16, block 1202 ) . 07-22-aia AIA Claim s 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash, in view of Kathawala , as applied to claim 1 above, and further in view of Chu et al. (US 9,721,671), hereinafter Chu . Regarding claim 2 , the combination of Prakash in view of Kathawala teaches the method of claim 1 , but fails to teach further comprising storing the device information in a plurality of latch circuits of the memory circuit . However, Chu, in an analogous art, teaches further comprising storing the device information in a plurality of latch circuits of the memory circuit ( Chu, col. 3, lines 31-35, “When a program command is issued, the write data is stored in latches associated with the memory cells. During programming, the latches of a memory cell can be read to determine the data state to which the cell is to be programmed” ) . Prakash, Kathawala, and Chu are considered to be analogous to the claimed invention because they are in the same field of utilizing verify voltage information in memory apparatuses/devices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Prakash in view of Kathawala to incorporate the teachings of Chu by including the functionality of storing device information in latch circuits. The suggestion/motivation for doing so would be to improve the reliability and accessibility of information during program and verify operations. Claim 12 is a memory device with limitations similar to the method of claim 2, and is rejected under the same rationale . 07-22-aia AIA Claim s 5-8 , 13, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash, in view of Kathawala , as applied to claim s 1 & 11 above, and further in view of Yoon (US 8,520,447) . Regarding claim 5 , the combination of Prakash in view of Kathawala teaches the method of claim 1 , but fails to teach wherein, further comprising setting the error status to indicate an error has occurred based on the level difference of the first verify voltage and the second verify voltage being outside of a reference range. However, Yoon, in an analogous art, teaches wherein, further comprising setting the error status to indicate an error has occurred based on the level difference of the first verify voltage and the second verify voltage being outside of a reference range ( Yoon, Fig. 2B & 2C teaches generating delta data [difference], comparing the delta data to reference data, generating a result based on the comparison, and determining pass/fail types from the comparison ) . Prakash, Kathawala, and Yoon are considered to be analogous to the claimed invention because they are in the same field of utilizing voltage information in memory apparatuses/devices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Prakash in view of Kathawala to incorporate the teachings of Yoon by including the functionality of indicating an error occurred based on level difference of verify voltages outside a reference range. The suggestion/motivation for doing so would be to provide a criteria for determining whether an error exists. Regarding claim 6 , the combination of Prakash in view of Kathawala, further in view of Yoon, teaches the method of claim 5, further comprising performing a refresh operation on the memory circuit under control of the controller ( Prakash, para. [0151], lines 23-29, “The control circuit is further configured to periodically apply a predetermined refresh read voltage to a selected one of the plurality of word lines for a predetermined period of time for each of the plurality of memory cells of the active subset at a specified interval to maintain the plurality of memory cells of the active subset in the second read condition [i.e., a refresh read operation]” ) based on the error status indicating the error ( Kathawala, Fig. 6C teaches detecting error conditions by comparing information derived from first and second threshold conditions ) . It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Prakash to incorporate the teachings of Kathawala by including the functionality of performing a refresh operation in response to detecting error conditions. The suggestion/motivation for doing so would be to restore memory reliability and improve the accuracy of subsequent operations. Regarding claim 7 , the combination of Prakash in view of Kathawala, further in view of Yoon, teaches the method of claim 6, further comprising: after the refresh operation on the memory circuit is performed, again receiving the program command, the address, and the data from the controller; and again performing the program operation on the selected word line according to the program command received after the refresh operation on the memory circuit is performed ( Prakash, para. [0159], lines 12-25, “the method further includes the step of periodically applying a predetermined refresh read voltage to a selected one of the plurality of word lines for a predetermined period of time for each of the plurality of memory cells of the active subset at a specified interval to maintain the plurality of memory cells of the active subset in the second read condition. The method proceeds by adjusting the verify voltage by one of the plurality of power on verify level offsets for the program operation of the plurality of memory cells of the active subset. The next step of the method is adjusting the verify voltage by one of the plurality of power off verify level offsets for the program operation of the plurality of memory cells of the passive subset” ) . Regarding claim 8 , the combination of Prakash in view of Kathawala, further in view of Yoon, teaches the method of claim 1, further comprising determining a pass state of the program operation based on the level difference of the first verify voltage and the second verify voltage being inside of a reference range ( Yoon, Fig. 2B & 2C teaches generating delta data [difference], comparing the delta data to reference data, generating a result based on the comparison, and determining pass/fail types from the comparison ). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Prakash in view of Kathawala to incorporate the teachings of Yoon by including the functionality of determining a pass state based on level differences of verify voltages inside a reference range. The suggestion/motivation for doing so would be to provide a criteria for determining whether an error exists. Regarding claim 13 , the combination of Prakash in view of Kathawala, further in view of Yoon, teaches the memory device of claim 11, wherein the error checker circuit comprises: a first register configured to store the first verify code ( Yoon, Fig. 2B teaches a page register 161b used along with a subtractor and comparator circuit for storing data used in the comparison operation; the page register equates to a register that stores information used in generating the comparison result ) ; a second register configured to store the second verify code ( Yoon, Fig. 2B teaches storing comparison inputs used by a subtractor and comparator circuitry that is associated with generating delta data and comparison results ; the stored comparison inputs equate to first and second values used to generate the delta value ) ; a delta code generator circuit configured to generate a delta code corresponding the level difference of the first verify code stored in the first register and the second verify code stored in the second register ( Yoon, Fig. 2B teaches a subtractor 161a, generating delta data, and delta data as output ; the subtractor equates to a delta code generator, the delta data equates to a delta code, and the subtraction operation equates to a level difference ) ; a reference range generator circuit configured to generate a maximum reference value and a minimum reference value, based on the device information ( Yoon teaches reference data and reference values supplied to the comparator circuitry ) ; and a comparator configured to identify a comparison result by determining whether the delta code is greater than the maximum reference value and determining whether the delta code is smaller than the minimum reference value ( Yoon, Fig. 2B teaches a comparator 161c that compared delta data with reference data and generates comparison results ) , and to output the error status based on the comparison result ( Yoon teaches pass/fail output and control logic based on the comparison result ) . Yoon does not explicitly teach a reference range generator, however a person of ordinary skill in the art would have understood that determining whether a delta value is acceptable would require a maximum and minimum value for the comparison value. Generating both maximum and minimum reference values represents a predictable variation of Yoon’s teaching of a reference value comparison operation to determine if a difference falls within an acceptable range. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Prakash in view of Kathawala to incorporate the teachings of Yoon by including the functionality of difference calculation and comparison circuitry The suggestion/motivation for doing so would be to improve the reliability of programming operations and verification operations. Claim 18 is a memory device with limitations similar to the method of claim 5, and is rejected under the same rationale. Claim 20 is a memory device with limitations similar to the method of claim 8, and is rejected under the same rationale . 07-22-aia AIA Claim s 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash, in view of Kathawala, further in view of Yoon , as applied to claim 8 above, and further in view of Park (US 11,495,319) . Regarding claim 9 , the combination of Prakash in view of Kathawala, further in view of Yoon, teaches the method of claim 8, but fails to teach further comprising storing status information, based on the error status and the pass state. However, Park, in an analogous art, teaches further comprising storing status information, based on the error status and the pass state ( Park, Fig. 8 ) . Prakash, Kathawala, Yoon, and Park are considered to be analogous to the claimed invention because they are in the same field of memory apparatuses/devices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Prakash in view of Kathawala, further in view of Yoon, to incorporate the teachings of Park by including the functionality of storing error status and pass state. The suggestion/motivation for doing so would be to improve memory reliability and system robustness. Regarding claim 10 , the combination of Prakash in view of Kathawala, further in view of Yoon, and further in view of Park, teaches the method of claim 9, further comprising: receiving a status read command from the controller; and transmitting the status information to the controller in response to the status read command ( Prakash, para. [0093], lines 16-19, “A memory interface 230 provides the command sequences to non-volatile memory die 108 and receives status information from the non-volatile memory die” ) . 07-22-aia AIA Claim s 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash, in view of Kathawala , as applied to claim s 14 & 16 above, and further in view of Park . Regarding claim 15 , the combination of Prakash in view of Kathawala teaches the memory device of claim 14, but fails to teach wherein the control logic circuit is further configured to set status information, based on the error status detected by the error checker circuit and the pass state determined by the pass/fail checker circuit. However, Park teaches wherein the control logic circuit is further configured to set status information, based on the error status detected by the error checker circuit and the pass state determined by the pass/fail checker circuit ( Park, Fig. 8 ) . Prakash, Kathawala, and Park are considered to be analogous to the claimed invention because they are in the same field of memory apparatuses/devices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Prakash in view of Kathawala, further in view of Yoon, to incorporate the teachings of Park by including the functionality of setting status information that is based on an error status and pass state. The suggestion/motivation for doing so would be to improve memory reliability and error/fault management. Regarding claim 19 , the combination of Prakash in view of Kathawala teaches the method of claim 18, but fails to teach further comprising stopping execution of remaining program loops among the plurality of program loops based on the error status indicating that the error occurs. However, Park teaches further comprising stopping execution of remaining program loops among the plurality of program loops based on the error status indicating that the error occurs. ( Park teaches integrity check failures, threshold determination, performing error handling operations, as well as stopping firmware executions as an example error-handling operation; col. 2, lines 18-19, “the error handling operation may include stopping execution of the firmware” ) . Prakash, Kathawala, and Park are considered to be analogous to the claimed invention because they are in the same field of memory apparatuses/devices. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Prakash in view of Kathawala, further in view of Yoon, to incorporate the teachings of Park by including the functionality of stopping the execution of remaining programming operations. The suggestion/motivation for doing so would be to improve memory reliability and reduce the occurrences of programming errors or data corruption . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Seong et al. (US 11,237,766) teaches monitoring memory operations using voltage variation information, threshold voltage information, and status information. Kumar et al. (US 2022/0254416) teaches memory reliability management, including refresh operations. Han (US 7,965,553) teaches verifying memory cell programming using multiple verify voltages and fail-bit counting to determining pass/fail states. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE V BRADEN whose telephone number is (703)756-5381. The examiner can normally be reached Mon-Fri: 9AM-5:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /G.V.B./Examiner, Art Unit 2112 /ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112 Application/Control Number: 19/040,550 Page 2 Art Unit: 2112 Application/Control Number: 19/040,550 Page 3 Art Unit: 2112 Application/Control Number: 19/040,550 Page 4 Art Unit: 2112 Application/Control Number: 19/040,550 Page 5 Art Unit: 2112 Application/Control Number: 19/040,550 Page 6 Art Unit: 2112 Application/Control Number: 19/040,550 Page 7 Art Unit: 2112 Application/Control Number: 19/040,550 Page 8 Art Unit: 2112 Application/Control Number: 19/040,550 Page 9 Art Unit: 2112 Application/Control Number: 19/040,550 Page 10 Art Unit: 2112 Application/Control Number: 19/040,550 Page 11 Art Unit: 2112 Application/Control Number: 19/040,550 Page 12 Art Unit: 2112 Application/Control Number: 19/040,550 Page 13 Art Unit: 2112 Application/Control Number: 19/040,550 Page 14 Art Unit: 2112 Application/Control Number: 19/040,550 Page 15 Art Unit: 2112 Application/Control Number: 19/040,550 Page 16 Art Unit: 2112 Application/Control Number: 19/040,550 Page 17 Art Unit: 2112 Application/Control Number: 19/040,550 Page 18 Art Unit: 2112
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