Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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1. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No. 12,253,959. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application would be anticipated by those of ‘959.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Grocutt (US 2021/0326134) in view of Espasa et al (US 2007/0094477, herein Espasa).
Grocutt teaches an integrated circuit for executing instructions comprising:
a processor core including a pipeline configured to execute instructions (Fig 1, [0057], processing circuitry);
a memory protection circuit configured to check for memory protection violations with a protection granule ([0059], [0061], memory protection unit 20); and
an index range circuit ([0083], memory attribute checking circuitry 16) configured to:
determine a range of addresses for a memory instruction that takes a vector register as a set of indices based on a base address of a vector in memory and a maximum bit width of the set of indices ([0068], [0081-0082], checking for memory protection violation according to address range based on a base address and variable size value); and
check, using the memory protection circuit during a single clock cycle, whether accessing elements of the vector within the range of addresses will cause a memory protection violation ([0082-0083], [0105], [0112], check for memory protection violations in a single instruction cycle).
Grocutt fails to teach wherein the instructions are specifically gather-scatter memory operations.
Espasa teaches an integrated circuit comprising a processor core including a pipeline configured to execute instructions, including gather-scatter memory instructions, and a memory protection circuit to check whether accessing elements of a vector within a range of addresses will cause a violation ([0023], processor cores, [0002], [0051-0053], gather/scatter operations, [0055], [0063], [0067], detecting conflicts in address ranges of gather or scatter operations).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Grocutt and Espasa to utilize the memory protection techniques for gather and scatter instructions. While Grocutt does not explicitly contemplate the use of gather or scatter instructions for accessing the memory system, both Grocutt and Espasa disclose techniques for handling memory protection in a processor that may utilize vector elements (Grocutt [0057], Espasa [0023]). As gather and scatter instructions are a routine and conventional aspect of vector processing, the combination would therefore merely entail a simple substitution of known prior art elements to achieve predictable results, and would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Grocutt and Espasa teaches the integrated circuit of claim 1, wherein the memory protection circuit is further configured to check two addresses per clock cycle (Grocutt [0105], checking two separate addresses).
Regarding claim 3, the combination of Grocutt and Espasa teaches the integrated circuit of claim 2, wherein the index range circuit is further configured to: input, during a single clock cycle, an address of a first byte of the range of addresses and an address of a last byte of the range of addresses to the memory protection circuit (Grocutt [0023], [0082], range checking based on array element byte size).
Regarding claim 4, the combination of Grocutt and Espasa teaches the integrated circuit of claim 1, wherein the memory protection circuit is further configured to check a single address per clock cycle (Grocutt [0105], checking single address).
Regarding claim 5, the combination of Grocutt and Espasa teaches the integrated circuit of claim 4, wherein the index range circuit is further configured to: check that the range of addresses falls within a single memory protection granule (Grocutt [0075], check address range against MPU entry that do not overlap).
Regarding claim 6, the combination of Grocutt and Espasa teaches the integrated circuit of claim 5, wherein the index range circuit is further configured to: input, during a single clock cycle, a single address in the range of addresses to the memory protection circuit (Grocutt [0105], single address checking).
Regarding claim 7, the combination of Grocutt and Espasa teaches the integrated circuit of claim 1, wherein the integrated circuit is further configured to: responsive to detection of a memory protection violation associated with an element of the vector, raise an exception (Grocutt [0065], trigger exception when violation encountered).
Regarding claim 8, the combination of Grocutt and Espasa teaches the integrated circuit of claim 1, wherein the integrated circuit is further configured to: responsive to detection of no memory protection violation associated with an element of the vector, access the element of the vector (claim 14, [0071], allow read/write access when permitted).
Claims 9-16 refer to a method embodiment of the circuit embodiment of claims 1-8. Therefore, the above rejections for claims 1-8 are applicable to claims 9-16, respectively.
Claims 17-20 refer to a storage media embodiment of claims 1-3 and 6. Therefore, the above rejections for claims 1-3 and 6 are applicable to claims 17-19 and 20, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Rash (US 2014/0281399) discloses a processor that checks for memory protection violations for a vector gather instruction.
Faanes (US 2002/0144061) discloses a processor that performs scatter-gather operations and checks multiple read addresses per clock cycle.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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