Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Objections
Claims 20: Antecedent issue found for the limitation "the second voltage". Appropriate correction is needed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-16 of U.S. Patent No. 11636914.
Current Application # 19041462
US Pat # 11636914
For example:
Claim 1:
1. A memory system, comprising: a non-volatile memory including a plurality of memory cells; and a memory controller configured to: store first data read from the plurality of memory cells in a storage circuit, the first data being read by using a first voltage; store second data read from a bit group including respective bits of the plurality of memory cells in a storage circuit, the second data being read by using a first read voltage group; perform an error correction of the second data; and determine, if third data is obtained as a result of successful error correction of the second data, a second read voltage group based on the first data stored in the storage circuit, the second data, and the third data.
For example:
Claim 1:
1. A memory system comprising: a non-volatile memory device; and a controller configured to execute an error correction process on first data read from a first area at a first address of the non-volatile memory device and determine a read level used for reading data at the first address according to a result of the correction process, wherein the controller is configured to execute the correction process on first frame data of the first data, when the correction process on the first frame data has failed, execute the correction process on second frame data of the first data, and when the correction process on the second frame data has succeeded, determine the read level based on a result of comparison between the second frame data and a result of the correction process on the second frame data.
2. The memory system according to claim 1, wherein when the correction process on the second frame data has failed, the controller is configured to read second data from a second area at a second address, execute the correction process on a third frame data of the second data, and determine the read level based on a result of comparison between the third frame data and a result of the correction process on the third frame data.
8. The memory system according to claim 1, wherein The controller is configured to among a plurality of memory cells in a storage area of the second frame data, count a first number of memory cells that have changed from a first threshold voltage lower than the read level to a second threshold voltage equal to or higher than the read level and a second number of memory cells that have changed from the second threshold voltage to the first threshold voltage, calculate a ratio between the first number and the second number, and calculate a shift amount of the read level based on the ratio.
Even though the claims at issue are not identical but overall scope of the claims are identical and they are not patentably distinct from each other.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Takada et al. (US Pub # 2022/0301653).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Takada et al. teach a memory system, comprising: a non-volatile memory including a plurality of memory cells; and a memory controller configured to: store first data read from the plurality of memory cells in a storage circuit, the first data being read by using a first voltage (see Fig.1-4, 6-37, paragraph 0044, 0052, claim 1-2, 5-15, 17-18, memory controller 100, first data read from first area and store in a buffer); store second data read from a bit group including respective bits of the plurality of memory cells in a storage circuit, the second data being read by using a first read voltage group; perform an error correction of the second data voltage (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358, 0415-0416, 0487-0488, 0506-0535, claim 1-2, 5-15, 17-18, second data read from second area and store in a buffer, error check and correction unit 160); and determine, if third data is obtained as a result of successful error correction of the second data, a second read voltage group based on the first data stored in the storage circuit, the second data, and the third data (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358, 0415-0416, 0487-0488, 0506-0535, claim 1-2, 5-15, 17-18, third data from third area).
Even though Takada et al. teach first read voltage and second read voltage but silent exclusively about read voltage group. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Takada et al. where multiple read voltage level AR, BR…GR and read reference voltage level VAR, VBR…VGR are used during reading operation which would be arranged into multiple group for reading in order to effective execute the operation and to improve success probability of error correction by efficiently detecting error and correcting error for the memory device (see paragraph 0748).
Regarding dependent claims 2, Takada et al. further teach wherein the memory controller is configured to determine the second read voltage group based on a first count and a second count of the second data based on comparison between the second data and the third data, the first count is a count of first bits of the third data in which a first-type error has been corrected, and the second count is a count of second bits of the third data in which a second-type error has been corrected (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358).
Regarding dependent claims 3, Takada et al. further teach wherein the first bits are bits that has a first value in the second data and has a second value in the third data, and the second bits are bits that has the second value in the second data and has the first value in the third data (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0347).
Regarding dependent claims 4, Takada et al. further teach wherein the memory controller determines the second read voltage group based on a voltage that makes a ratio between the first count and the second count close to 1. (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332).
Regarding dependent claims 5, Takada et al. further teach wherein the second read voltage group includes a first read voltage and a second read voltage, and the memory controller is configured to: acquire, based on the first data stored in the storage circuit, the second data, and the third data, a third count of the first bits of the third data, a fourth count of the first bits of the third data, a fifth count of the second bits of the third data, and a sixth count of the second bits of the third data; determine the first read voltage based on the third count and the fifth count; and determine the second read voltage based on the fourth count and the sixth count. (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358, 0415-0416).
Regarding dependent claims 6, Takada et al. further teach wherein the first read voltage group includes a third read voltage and a fourth read voltage, and the memory controller is configured to: store a plurality of items of fourth data read from the bit group in a storage circuit, the plurality of items of fourth data being read using a plurality of third read voltage groups; generate a plurality of items of fifth data and a plurality of items of sixth data from the plurality of items of fourth data using the first data; determine the third read voltage based on the plurality of items of fifth data; and determine the fourth read voltage based on the plurality of items of sixth data (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358, 0415-0416).
Regarding dependent claims 7, Takada et al. further teach wherein the non-volatile memory further includes a word line coupled to the plurality of memory cells, the non-volatile memory is configured to read the first data by applying the first read voltage and to send the first data to the memory controller, and the memory controller is configured to acquire the first data by receiving the first data. (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358, 0415).
Regarding dependent claims 8, Takada et al. further teach wherein the non-volatile memory further includes a word line coupled to the plurality of memory cells, the non-volatile memory is configured to read the second data by applying the third read voltage and the fourth read voltage and to send the second data to the memory controller, and the memory controller is configured to acquire the second data by receiving the second data (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332).
Regarding independent claim 9, Takada et al. teach a memory system, comprising: a non-volatile memory including a plurality of memory cells; a memory controller configured to: store a plurality of items of first data read from a bit group including respective bits of the plurality of memory cells in a storage unit, the plurality of items of first data being read using a plurality of different first read voltage groups (see Fig.1-4, 6-37, paragraph 0044, 0052, claim 1-2, 5-15, 17-18, memory controller 100, first data read from first area and store in a buffer); determine a second read voltage group using the plurality of items of first data; store second data read from the bit group in a storage circuit, the second data being read using the second read voltage group (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358, 0415-0416, 0487-0488, 0506-0535, claim 1-2, 5-15, 17-18, second data read from second area and store in a buffer, error check and correction unit 160); acquire, if third data is obtained as a result of error correction of the second data, a plurality of first counts and a plurality of second counts based on the plurality of items of first data and the third data; and determine a third read voltage group based on comparison between the plurality of first counts and the plurality of second counts. (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358, 0415-0416, 0487-0488, 0506-0535).
Even though Takada et al. teach first read voltage and second read voltage but silent exclusively about read voltage group. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Takada et al. where multiple read voltage level AR, BR…GR and read reference voltage level VAR, VBR…VGR are used during reading operation which would be arranged into multiple group for reading in order to effective execute the operation and to improve success probability of error correction by efficiently detecting error and correcting error for the memory device (see paragraph 0748).
Regarding dependent claims 10, Takada et al. further teach wherein the plurality of first counts have a first relationship that has a distribution for magnitudes of read voltages used in the read from the bit group, the plurality of second counts have a second relationship that has a distribution for magnitudes of read voltages used in the read from the bit group, each of the plurality of first counts is a count of first bits of one of the plurality of items of first data in which a first-type error has been corrected, each of the plurality of second counts is a count of second bits of one of the plurality of items of first data in which a second-type error has been corrected, and the memory controller determines the third read voltage group based on the first relationship and the second relationship (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358).
Regarding dependent claims 11, Takada et al. further teach wherein the first bits are bits that has a first value in the second data and has a second value in the third data, and the second bits are bits that has the second value in the second data and has the first value in the third data (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331).
Regarding dependent claims 12, Takada et al. further teach wherein the second read voltage group includes a first read voltage and a second read voltage, the third read voltage group includes a third read voltage and a fourth read voltage, the memory controller is configured to: store fourth data read from the plurality of memory cells in a storage unit, the fourth data being read using a first voltage; generate a plurality of items of fifth data and a plurality of items of sixth data from the plurality of -6- items of first data using the fourth data (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139); determine the first read voltage based on the plurality of items of fifth data; determine the second read voltage based on the plurality of items of sixth data; and generate a plurality of items of seventh data and a plurality of items of eighth data from the plurality of items of first data, the third data, and the fourth data, wherein each of the plurality of first counts is a count of first bits of one of the plurality of items of seventh data, and each of the plurality of second counts is a count of second bits of one of the plurality of items of eighth data (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358, 0415-0416, 0487).
Regarding dependent claims 13, Takada et al. further teach configured to store the plurality of items of first data up to an intermediate stage of the generating of the plurality of items of seventh data and the plurality of items of eighth data; and a second storage circuit configured to store the fourth data until completion of the generating of the plurality of items of seventh data and the plurality of items of eighth data (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134).
Regarding dependent claims 14, Takada et al. further teach wherein the second read voltage group includes a first read voltage and a second read voltage, the third read voltage group includes a third read voltage and a fourth read voltage, the memory controller is configured to: store fourth data read from the plurality of memory cells in a storage circuit, the fourth data being read using a first voltage; generate a plurality of items of fifth data and a plurality of items of sixth data from the plurality of items of first data using the fourth data; determine the first read voltage based on the plurality of items of fifth data (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139); determine the second read voltage based on the plurality of items of sixth data; generate a plurality of items of ninth data and a plurality of items of tenth data based on the third data and the plurality of items of fifth data; and generate a plurality of items of eleventh data and a plurality of items of twelfth data based on the third data and the plurality of items of sixth data, each of the plurality of first counts is a count of bits of one of the plurality of items of ninth data and the plurality of items of eleventh data in which a first-type error has been corrected, and each of the plurality of second counts is a count of bits of one of the plurality of items of tenth data and the plurality of items of twelfth data in which a second-type -8- error has been corrected (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358, 0415-0416, 0487-0488, 0506-0535).
Regarding independent claim 15, Takada et al. teach a memory system, comprising: a non-volatile memory including a plurality of memory cells; and a memory controller configured to: store a plurality of items of first data read from a bit group including respective bits of the plurality of memory cells in a storage circuit, the plurality of items of first data being read using a plurality of first read voltage groups (see Fig.1-4, 6-37, paragraph 0044, 0052, claim 1-2, 5-15, 17-18, memory controller 100, first data read from first area and store in a buffer); determine a second read voltage group using the plurality of items of first data; store second data read from the bit group in a storage circuit, the second data being read using the second read voltage group (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358, 0415-0416, 0487-0488, 0506-0535, claim 1-2, 5-15, 17-18, second data read from second area and store in a buffer, error check and correction unit 160); and perform, if error correction of the second data fails, an error correction of fifth data including a first portion of third data of one of the plurality of items of first data and a second portion of fourth data of one of the plurality of items of first data, wherein the third data and the fourth data differ from each other, and the first portion and the second portion differ from each other (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358, 0415-0416, 0487-0488, 0506-0535).
Even though Takada et al. teach first read voltage and second read voltage but silent exclusively about read voltage group. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Takada et al. where multiple read voltage level AR, BR…GR and read reference voltage level VAR, VBR…VGR are used during reading operation which would be arranged into multiple group for reading in order to effective execute the operation and to improve success probability of error correction by efficiently detecting error and correcting error for the memory device (see paragraph 0748).
Regarding dependent claims 16, Takada et al. further teach wherein the first portion of the third data includes a plurality of bits of one of the plurality of items of first data classified into a first group based on a first standard,the second portion of the fourth data includes a plurality of bits of one of the plurality of items of first data classified into a second group based on the first standard, and the first group and the second group differ from each other. (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358).
Regarding dependent claims 17, Takada et al. further teach wherein the memory controller is configured to store sixth data read from the plurality of memory cells in a storage circuit, the sixth data being read using a first voltage,the first portion of the third data includes a plurality of bits classified into the first group based on one of the plurality of items of first data and the sixth data, and the second portion of the fourth data includes a plurality of bits classified into the second group based on one of the plurality of items of first data and the sixth data. (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259).
Regarding dependent claims 18, Takada et al. further teach wherein the plurality of bits classified into the first group contain data based on one of the plurality of memory cells determined to have a threshold voltage lower than the first voltage, and the plurality of bits classified into the second group contain data based on one of the plurality of memory cells determined to have a threshold voltage equal to or higher - 10 - than the first voltage (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332).
Regarding dependent claims 19, Takada et al. further teach wherein the non-volatile memory further includes a plurality of second memory cells, the memory controller is configured to store seventh data read from the plurality of second memory cells in a storage circuit, the seventh data being read using a second voltage, the first portion of the third data includes, from one of the plurality of items of first data, a plurality of bits classified into a first group based on the seventh data, and the second portion of the fourth data includes, from one of the plurality of items of first data, a plurality of bits classified into a second group based on the seventh data (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358, 0415-0416).
Regarding dependent claims 20, Takada et al. further teach wherein the plurality of bits classified into the first group contain data based on one of the plurality of memory cells adjacent to one of the plurality of second memory cells determined to have a threshold voltage lower than the second voltage, and the plurality of bits classified into the second group contain data based on one of the plurality of memory cells determined to have a threshold voltage equal to or higher than the second voltage (see Fig.1-4, 6-37, paragraph 0034-0039, 0044, 0052, 0054-0057, 0064-0071, 0134-0139, 0187-0198, 0210-0216, 0236-0259, 0328, 0331-0332, 0346-0358).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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