DETAILED ACTION
This office action is in response to an Amendment/Request for Reconsideration-After Non-Final rejection filed 7/16/2026 for application 19/041,844 filed 1/30/2025 that is a continuation of 18/046,100 and claims priority to KR10-2021-0161074 filed 11/22/2021.
Claims 1 and 11 have been amended. No claims are new. No claims have been canceled. Thus, claims 1-20 have been examined.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, and 7-9 are rejected under U.S.C. 102(a)(1) and (a)(2) as being unpatentable over Cutress (An article titled “Did IBM Just Preview The Future of Caches?” by Dr. Ian Cutress, published Sept 2, 2021” downloaded from archive.org on 11/19/2021) in view of McGregor (An article titled “IBM Re-Architects The Mainframe With New Telum Processor” by Jim McGregor, et al., published Aug 23, 2021 and attached to this office action.)
Regarding claim 1, Cutress teaches A system-on-chip (Cutress, page 1, lines 6-12, that discloses a Telum chip that is a system on a chip.) having a reconfigurable on-chip memory mounted thereon, (Cutress page 4 lines 3-39 that discloses 32 MB of each core is a mix of private L2 cache and shared L3 cache that may be reconfigured depending on the workload.) comprising: a plurality of processing units; (Cutress page 4 lines 3-39 discloses the chip may have eight cores) and an on-chip memory (Cutress page 4 lines 3-39 discloses 8 cores, each with 32 MB of L2 cache on a SOC.)
comprising a dedicated area for each of the plurality of processing units (Cutress page 4 lines 3-39 discloses an L2 cache area that is dedicated to a single core, for each core and the collection of all dedicated areas comprises a dedicated area for each of the plurality of processing units.) and a common area shared by at least two(2) of the plurality of processing units, (Cutress page 4 lines 3-39 discloses a portion of the 32 MB of each core memory is shared L3 cache for other caches to use when their L2 cache is full and they require more space. The collection of L2 cache data functioning as L3 shared cache is an example of a common area shared by at least two of the plurality of processing units.)
wherein a size of the dedicated area and a size of the common area change during runtime. (Cutress page 4 lines 3-39 discloses the size of the area dedicated to L3 cache for other processors to use is allocated as needed depending on the workload . Cutress page 6 lines 3-9 discloses that when a system needs data from a different core’s L2 cache, it acquires the memory by tagging the memory as a L3 cache line which is done in real time, thus during runtime (i.e. when the system is running).)
However, Cutress does not explicitly teach and wherein the on-chip memory in the dedicated area accesses each of the plurality of processing units directly and the on-chip memory in the common area shared by at least two of the plurality of processing units accesses the plurality of processing units via a data bus coupled with the system-on-chip.
McGregor, of a similar field of endeavor, further teaches and wherein the on-chip memory in the dedicated area accesses each of the plurality of processing units directly and the on-chip memory in the common area shared by at least two of the plurality of processing units accesses the plurality of processing units via a data bus coupled with the system-on-chip. (Consistent with para [0167] of the instant application directly accessing a memory is avoiding the use of a specified bus such as data bus 3000. McGregor page 3, lines 18-28 as well as the IBM Z Telum processor die photo with the bi-directional ring discloses that the system communicates using a bi-directional ring bus to communicate between the L2 caches for separate cores (i.e. the on-chip memory in the common area shared by at least two of the plurality of processing units), and does not use this bi-directional ring bus to communicate with the dedicated area (the L2 cache area dedicated to any given core), thus is directly communicating with the dedicated L2 cache for any given core.. Thus the core is communicating with the dedicated on-chip L2 memory directly, and communicated with the L2 memory shared by at least two of the other cores (i.e. processing units) using the bi-directional ring bus, where the bi-directional ring bus is an example of a data bus that communicates cache data between cores).
Cutress and McGregor are in a similar field of endeavor as both describe the architecture of the IBM Telum chip. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the details of how the bi-directional ring is used as taught by McGregor into the solution of Cutress that describes the key concepts of the IBM Telum chip, but not explicitly detail that the bi-directional ring is used only when communicating between cores, thus is directly communicating with the dedicated area of its L2 cache, and communicating using a data base when communicating between cores. Thus, combining prior art elements according to known methods (the details of the bus implementation as taught by McGregor for the IBM Telum chip into the architectural description of the IBM Telum chip as taught by Cutress) to yield predictable results (to have a greater understanding of the IBM Telum chip design).
The motivation to combine McGregor into the solution of Cutress for claims 2-10 are the same as set forth in claim 1 above.
Regarding claim 2, Cutress and McGregor teaches all of the limitations of claim 1 above.
Cutress further teaches a plurality of scratch pads included in the dedicated area; (Consistent with paras [0106]-[0107] a scratch pad memory area may be a memory location that is a private memory. Cutress page 4 lines 3-39 discloses 256 cores, each has 32 MB of private L2 cache that functions as a private L2 cache (thus is an example of a scratch pad that is in the dedicated area.).and a plurality of memory units included in the dedicated area or the common area. (Consistent with paras [0106]-[0107] a memory unit may be a portion of memory. Cutress page 4 lines 3-39 discloses 256 cores, each has 32 MB of private L2 cache that functions as a private L2 cache, thus each private L2 cache contains a portion of memory, thus is one or more memory units.).
Regarding claim 4, Cutress and McGregor teaches all of the limitations of claim 2 above. Cutress further teaches wherein the plurality of memory units includes at least one first memory unit included in the dedicated area and at least one second memory unit included in the common area, (Cutress page 5 line 3 through page line 12 as detailed above where each CPU contains L2 memory that is a portion of memory that is dedicated and a portion of memory that is shared.) the at least one first memory unit operates in a scratch pad type, (Consistent with paras [0106]-[0107] a scratch pad memory area may be a memory location in a private memory area. (Cutress page 4 lines 3-39 discloses an L2 cache area that is dedicated to a single core, for each core thus is an example of a scratchpad memory that operates in a scratch pad type.) and the at least one second memory unit operates in a shared memory type. (Cutress page 4 lines 3-39 that discloses a portion of the 32 MB of each core memory is shared L3 cache for other caches to use when their L2 cache is full and they require more space.)
Regarding claim 5, Cutress and McGregor teaches all of the limitations of claim 4 above. Cutress further teaches wherein, during runtime, at least one of the at least one first memory unit changes operation to the shared memory type and is included in the common area. (Cutress page 4 lines 3-39 discloses the size of the area dedicated to L3 cache for other processors to use is allocated as needed depending on the workload . Cutress page 4 lines 3-39 discloses that when a system needs data from a different core’s L2 cache, it acquires the memory by tagging the memory as a L3 cache line which is done in real time, thus during runtime (i.e. when the system is running).)
Regarding claim 7, Cutress and McGregor teaches all of the limitations of claim 4 above. Cutress further teaches wherein a first scratch pad among the plurality of scratch pads included in the dedicated area and a memory unit among the at least one first memory unit corresponding to the first scratch pad logically operate as a single scratch pad memory. (Examiner notes that the instant application does not contain an explicit definition of logically operated and the term may simply mean that the scratch pad is identified as a single scratch pad memory. The dedicated L2 memory that is private to a single cpu may be identified as a single scratch pad memory as the memory is identified as a single logical entity (the private memory for the cache). See Cutress page 4 lines 3-39 as detailed in claim 1 above.)
Regarding claim 8, Cutress and McGregor teaches all of the limitations of claim 4 above. Cutress further teaches wherein the at least one first memory unit is shared by two(2) processing units and by two scratch pads respectively corresponding to the two(2) processing units. (Cutress page 4 lines 3-39 teaches a set of private L2 cache memories that form a first memory unit, and this set of private cache memories is shared with two processing units and is used to form two scratch pads, one scratch pad per CPU (i.e. each scratch pad corresponding to one of two processing units).)
Regarding claim 9, Cutress and McGregor teaches all of the limitations of claim 4 above. Cutress further teaches wherein a ratio between the at least one first memory unit and the at least one second memory unit is adjustable. (Cutress page 4 lines 3-39 discloses the size of the area dedicated to L3 cache for other processors to use is allocated as needed depending on the workload . Cutress page 4 lines 3-39 discloses that when a system needs data from a different core’s L2 cache, it acquires the memory by tagging the memory as a L3 cache line which is done in real time, thus during runtime (i.e. when the system is running). Thus the ratio of data in the private area is decreasing and the area in one or more shared area is increasing and the ratio is adjustable.)
Claims 3, 11-15, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Cutress (An article titled “Did IBM Just Preview The Future of Caches?” by Dr. Ian Cutress, published Sept 2, 2021” downloaded from archive.org on 11/19/2021) ) in view of McGregor (An article titled “IBM Re-Architects The Mainframe With New Telum Processor” by Jim McGregor, et al., published Aug 23, 2021 and attached to this office action.) as detailed above and further in view of Labbe (LABBE et al., US 2020/0051309 A1).
Regarding claim 3, Cutress and McGregor teaches all of the limitations of claim 1 above. However, the combination does not explicitly teach deep learning, thus does not explicitly teach wherein each of a first calculation task processed by at least one of the plurality of processing units and a second calculation task processed by at least one other processing unit of the plurality of processing units includes at least one of a deep learning training task or a deep learning inference task.
Labbe, of a similar field of endeavor, further teaches wherein each of a first calculation task processed by at least one of the plurality of processing units and a second calculation task processed by at least one other processing unit of the plurality of processing units includes at least one of a deep learning training task or a deep learning inference task. (Consistent with paragraph [0088] of the instant application, a task associated with neural networks is an example of a deep learning task. Labbe [0198]-[0201] discloses that the Graphics Processor such as the graphics processor 108 of Fig. 1 may perform neural network pipeline operations using L1, L2, L3, or L4 caches. Thus the solution of Curtis and McGregor in view of Labbe be directed to a graphic operations that accelerate operations using resources such as L2 and L3 caches associated with graphic neural network pipelines (Labbe [0199]).)
Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the neural network pipeline operations that are performed on GPUs in cooperation with L2 and L3 caches as taught by Labbe and accelerated by dynamic L2 and L3 caches as taught by Cutress and McGregor. Thus combining prior art elements according to known methods to achieve predictable results (accelerating operations associated with graphic neural network pipelines that use L2 and L3 caches).
Regarding claim 11, Cutress teaches A method of using a system-on-chip having a reconfigurable on-chip memory mounted thereon (Cutress page 4 lines 3-39 teaches a concept that each L2 cache is a private cache for each core and contains a separate area to share space with different L2 cores that is adjusted based on the workload, thus is directed to a method on a SOC having reconfigurable on-chip memory)
and comprising a plurality of processing units, (Cutress page 4 lines 3-39 discloses the chip may have eight cores)
and changing, during runtime, a size of a dedicated area for each of the plurality of processing units and a size of a common area shared by at least two(2) of the plurality of processing units. (Cutress page 4 lines 3-39 discloses the size of the area dedicated to L3 cache for other processors to use is allocated as needed depending on the workload . Cutress page 4 lines 3-39 discloses that when a system needs data from a different core’s L2 cache, it acquires the memory by tagging the memory as a L3 cache line which is done in real time, thus during runtime (i.e. when the system is running) and is changing the size of dedicated area and the size of common area.)
However, Cutress does not explicitly teach the method comprising: assigning a first calculation task to at least one first processing unit of the plurality of processing units; assigning a second calculation task to at least one second processing unit of the plurality of processing units; … and wherein the on-chip memory in the dedicated area accesses each of the plurality of processing units directly and the on-chip memory in the common area shared by at least two of the plurality of processing units accesses the plurality of processing units via a data bus coupled with the system-on-chip.
McGregor, of a similar field of endeavor, further teaches and wherein the on-chip memory in the dedicated area accesses each of the plurality of processing units directly and the on-chip memory in the common area shared by at least two of the plurality of processing units accesses the plurality of processing units via a data bus coupled with the system-on-chip. (Consistent with para [0167] of the instant application directly accessing a memory is avoiding the use of a specified bus such as data bus 3000. McGregor page 3, lines 18-28 as well as the IBM Z Telum processor die photo with the bi-directional ring discloses that the system communicates using a bi-directional ring bus to communicate between the L2 caches for separate cores (i.e. the on-chip memory in the common area shared by at least two of the plurality of processing units), and does not use this bi-directional ring bus to communicate with the dedicated area (the L2 cache area dedicated to any given core), thus is directly communicating with the dedicated L2 cache for any given core.. Thus the core is communicating with the dedicated on-chip L2 memory directly, and communicated with the L2 memory shared by at least two of the other cores (i.e. processing units) using the bi-directional ring bus, where the bi-directional ring bus is an example of a data bus that communicates cache data between cores).
Cutress and McGregor are in a similar field of endeavor as both describe the architecture of the IBM Telum chip. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the details of how the bi-directional ring is used as taught by McGregor into the solution of Cutress that describes the key concepts of the IBM Telum chip, but not explicitly detail that the bi-directional ring is used only when communicating between cores, thus is directly communicating with the dedicated area of its L2 cache, and communicating using a data base when communicating between cores. Thus, combining prior art elements according to known methods (the details of the bus implementation as taught by McGregor for the IBM Telum chip into the architectural description of the IBM Telum chip as taught by Cutress) to yield predictable results (to have a greater understanding of the IBM Telum chip design).
The motivation to combine McGregor into Cutress for claims 12-13 is the same as set forth in claim 11 above.
However, the combination of Cutress and McGregor does not explicitly teach the method comprising: assigning a first calculation task to at least one first processing unit of the plurality of processing units; assigning a second calculation task to at least one second processing unit of the plurality of processing units;
Labbe, of a similar field of endeavor, further teaches the method comprising: assigning a first calculation task to at least one first processing unit of the plurality of processing units; assigning a second calculation task to at least one second processing unit of the plurality of processing units; (Labbe [0152] discloses a general-purpose processing unit (GPGPU) receives commands from the host and uses a scheduler to distribute execution threads associated with those commands to a set of compute clusters 1436A-1436H, each of which is a graphics processing unit.)
Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the neural network pipeline operations that are performed in parallel on GPUs in cooperation with L2 and L3 caches as taught by Labbe and accelerated by dynamic L2 and L3 caches as taught by Cutress and McGregor. Thus combining prior art elements according to known methods to achieve predictable results (accelerating operations associated with graphic neural network pipelines that use L2 and L3 caches).
The motivation to combine Labbe into Cutress and McGregor for claims 11-20 are the same as those set forth in claim 11 above.
Regarding claim 12, the combination of Cutress, McGregor, and Labbe teaches all of the limitations of claim 11 above.
The remainder of claim 12 recites limitations described in claim 2 above and thus is rejected based on the teaching and rationale of claim 2 above.
Regarding claim 13, the combination of Cutress, McGregor, and Labbe teaches all of the limitations of claim 11 above.
The remainder of claim 13 recites limitations described in claim 3 above and thus is rejected based on the teaching and rationale of claim 3 above.
Regarding claim 14, the combination of Cutress, McGregor, and Labbe teaches all of the limitations of claim 12 above.
further comprising: operating, at least one first memory unit of the plurality of memory units included in the dedicated area, in a scratch pad type; (Cutress page 5 line 3 through page 6 line 12 discloses an L2 cache area that is dedicated to a single core, for each core and the collection of all dedicated areas comprises a dedicate area for each of the plurality of processing units and operating the portion in the private area is operating in a scratch pad type.) and operating, at least one second memory unit of the plurality of memory units included in the common area, in a shared memory type. (Cutress page 4 lines 3-39 that discloses a portion of the 32 MB of each core memory is shared L3 cache for other caches to use when their L2 cache is full and they require more space. The collection of L3 cache is an example of a common area shared by at least two of the plurality of processing units.)
Regarding claim 15, the combination of Cutress, McGregor, and Labbe teaches all of the limitations of claim 14 above. Cutress further teaches wherein the changing the size of the dedicated area and the size of the common area during runtime comprises, changing, an operation of at least one of the at least one first memory unit, to the shared memory type during runtime. (Cutress page 4 lines 3-39 discloses the size of the area dedicated to L3 cache for other processors to use is allocated as needed depending on the workload . Cutress page 4 lines 3-39 discloses that when a system needs data from a different core’s L2 cache, it acquires the memory by tagging the memory as a L3 cache line which is done in real time, thus during runtime (i.e. when the system is running). Thus is changing the size of both the dedicated and common area during runtime.)
Regarding claim 17, the combination of Cutress, McGregor, and Labbe teaches all of the limitations of claim 14 above.
The remainder of claim 17 recites limitations described in claim 7 above and thus is rejected based on the teaching and rationale of claim 7 above.
Regarding claim 18, the combination of Cutress, McGregor, and Labbe teaches all of the limitations of claim 14 above.
The remainder of claim 18 recites limitations described in claim 8 above and thus is rejected based on the teaching and rationale of claim 8 above.
Regarding claim 19, the combination of Cutress, McGregor, and Labbe teaches all of the limitations of claim 14 above.
Cutress further teaches wherein the changing the size of the dedicated area and the size of the common area during runtime comprises adjusting a ratio between the at least one first memory unit and the at least one second memory unit. (Cutress page 4 lines 3-39 discloses the size of the area dedicated to L3 cache for other processors to use is allocated as needed depending on the workload . Cutress page 4 lines 3-39 discloses that when a system needs data from a different core’s L2 cache, it acquires the memory by tagging the memory as a L3 cache line which is done in real time, thus during runtime (i.e. when the system is running). Thus the ratio of data in the private area is decreasing and the area in one or more shared area is increasing and the ratio is adjustable.)
Claim 6, 10, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Cutress (An article titled “Did IBM Just Preview The Future of Caches?” by Dr. Ian Cutress, published Sept 2, 2021” downloaded from archive.org on 11/19/2021) in view of McGregor (An article titled “IBM Re-Architects The Mainframe With New Telum Processor” by Jim McGregor, et al., published Aug 23, 2021 and attached to this office action.) as detailed above and further in view of Davis (Davis et al., US 2016/0179717 A1)
Regarding claim 6, Cutress and McGregor teaches all of the limitations of claim 4 above. However, the combination does not explicitly teach wherein, during runtime, at least one of the at least one second memory unit changes operation to the scratch pad type and is included in the dedicated area.
Davis, of a similar field of endeavor, further teaches wherein, during runtime, at least one of the at least one second memory unit changes operation to the scratch pad type and is included in the dedicated area. (Davis [0026]-[0027] teaches that resources may be rerouted to different physical layers (such as a different cache level, due to workload changes. Thus Davis suggests moving cache from a L3 layer to a L2 layer, and Cutress in view of Davis would move data from shared space (its virtual L3 layer) to its private space in the L2 layer based on workload changes.)
Cutress, McGregor, and Davis are in a similar field of endeavor, as all relate to managing dynamic memory regions. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the Management Compute Subsystem of Davis that controls access to shared cache resources according to work load demand into the solution of Cutress and McGregor that manages shared memory resources according to work load demand. Thus combining prior art elements according to known methods to produce predictable results (manage access to shared resources and adjust the workload to various work load demand to more closely match the applications needs with the available resources. See Davis [0027])
Regarding claim 10, Cutress and McGregor teaches all of the limitations of claim 2 above. Cutress further teaches wherein, the plurality of memory units includes at least one first memory unit included in the dedicated area and at least one second memory unit included in the common area, (Cutress page 4 lines 3-39 as detailed in claim 1 above.)
However, the combination does not explicitly teach a controller, thus does not explicitly teach at least one first memory unit included in the dedicated area is controlled by a scratch pad controller that controls data exchange between a memory unit and a scratch pad, and at least one second memory unit included in the common area is controlled by a global controller that controls data exchange between a memory unit and a data bus.
Davis, of a similar field of endeavor, further teaches at least one first memory unit included in the dedicated area is controlled by a scratch pad controller that controls data exchange between a memory unit and a scratch pad, (Davis Fig. 6 and para [0023] discloses the management compute subsystem manages resources for the server compute subsystem which include the memory resources L1, 2, and L3 caches. Thus the Management Compute Subsystem of Cutress in view of Davis would control data in the private L2 Caching areas (the scratch pad) for each core)
and at least one second memory unit included in the common area is controlled by a global controller (Davis Fig. 6 and para [0023] discloses the management compute subsystem manages resources for the server compute subsystem which include the memory resources L1, 2, and L3 caches. Thus the Management Compute Subsystem of Cutress in view of Davis would control the shared L2 cache area (a second memory unit included in the common area) and thus is an example of a global controller.) that controls data exchange between a memory unit and a data bus. (Davis [0028] and [0040] discloses a fabric bridge provides routing between processor cores, memory controllers may connect the L1/L2 Caches within the Server Compute System and the multi-core processors share resources such as buses with the L1 and /or L2 cache which would include both data and control buses.)
Cutress, McGregor, and Davis are in a similar field of endeavor, as all relate to managing dynamic private and share memory regions. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the Management Compute Subsystem of Davis that controls access to shared cache resources according to work load demand into the solution of Cutress and McGregor that manages shared memory resources according to work load demand. Thus combining prior art elements according to known methods to produce predictable results (manage access to shared resources and adjust the workload to various work load demand to more closely match the applications needs with the available resources. See Davis [0027])
Regarding claim 16, the combination of Cutress, McGregor, and Labbe teaches all of the limitations of claim 14 above. However, the combination does not explicitly disclose wherein the changing the size of the dedicated area and the size of the common area during runtime comprises, changing, an operation of at least one of the at least one second memory unit, to the scratch pad type during runtime.
Davis, of a similar field of endeavor, further discloses wherein the changing the size of the dedicated area and the size of the common area during runtime comprises, changing, an operation of at least one of the at least one second memory unit, to the scratch pad type during runtime. (Davis [0026]-[0027] teaches that resources may be rerouted to different physical layers (such as a different cache level, due to workload changes. Thus Davis suggests moving cache from a L3 layer to a L2 layer, and Cutress in view of Davis would move data from shared space (its virtual L3 layer) to its private space in the L2 layer based on work load changes.)
Cutress, McGregor, Labbe, and Davis are in a similar field of endeavor, as all relate to managing dynamic private and share memory regions. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the Management Compute Subsystem of Davis that controls access to shared cache resources according to work load demand into the solution of Cutress, McGregor, and Labbe that manages shared memory resources according to work load demand. Thus combining prior art elements according to known methods to produce predictable results (manage access to shared resources and adjust the workload to various work load demand to more closely match the applications needs with the available resources. See Davis [0027])
Claim 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cutress (An article titled “Did IBM Just Preview The Future of Caches?” by Dr. Ian Cutress, published Sept 2, 2021” downloaded from archive.org on 11/19/2021) in view of McGregor (An article titled “IBM Re-Architects The Mainframe With New Telum Processor” by Jim McGregor, et al., published Aug 23, 2021 and attached to this office action.) and Labbe (LABBE et al., US 2020/0051309 A1) as detailed in claim 12 above and further in view of Davis (Davis et al., US 2016/0179717 A1).
Regarding claim 20, the combination of Cutress, McGregor, and Labbe teaches all of the limitations of claim 12 above. Cutress further teaches wherein, the plurality of memory units includes at least one first memory unit included in the dedicated area and at least one second memory unit included in the common area, (Cutress page 4 lines 3-39 as detailed in claim 1 above.)
However, Cutress, McGregor, and Labbe does not explicitly teach a controller, thus does not explicitly teach the at least one first memory unit included in the dedicated area is controlled by a scratch pad controller that controls data exchange between a memory unit and a scratch pad, and at least one second memory unit included in the common area is controlled by a global controller that controls data exchange between a memory unit and a data bus.
Davis, of a similar field of endeavor, further teaches the at least one first memory unit included in the dedicated area is controlled by a scratch pad controller that controls data exchange between a memory unit and a scratch pad, (Davis Fig. 6 and para [0023] discloses the management compute subsystem manages resources for the server compute subsystem which include the memory resources L1, 2, and L3 caches. Thus the Management Compute Subsystem of Cutress in view of Davis would control data in the private L2 Caching areas (the scratch pad) for each core)
and at least one second memory unit included in the common area is controlled by a global controller (Davis Fig. 6 and para [0023] discloses the management compute subsystem manages resources for the server compute subsystem which include the memory resources L1, 2, and L3 caches. Thus the Management Compute Subsystem of Cutress in view of Davis would control the shared L2 cache area (a second memory unit included in the common area) and thus is an example of a global controller.) that controls data exchange between a memory unit and a data bus. (Davis [0028] and [0040] discloses a fabric bridge provides routing between processor cores, memory controllers may connect the L1/L2 Caches within the Server Compute System and the multi-core processors share resources such as buses with the L1 and /or L2 cache which would include both data and control buses.)
Cutress, McGregor, Labbe, and Davis are in a similar field of endeavor, as all relate to managing dynamic private and share memory regions. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the Management Compute Subsystem of Davis that controls access to shared cache resources according to work load demand into the solution of Cutress and Labbe that manages shared memory resources according to work load demand. Thus combining prior art elements according to known methods to produce predictable results (manage access to shared resources and adjust the workload to various work load demand to more closely match the applications needs with the available resources. See Davis [0027])
Response to Remarks
Examiner thanks applicant for their claim amendments and Remarks of 7/16/2026. They have been fully considered.
Examiner agrees that Cutress alone fails to explicitly teach "wherein the on-chip memory in the dedicated area accesses each of the plurality of processing units directly and the on-chip memory in the common area shared by at least two of the plurality of processing units accesses the plurality of processing units via a data bus coupled with the system-on-chip". Therefore the rejections have been withdrawn. However, upon further consideration and in response to the claims as amended, a new ground(s) of rejection is made in view of McGregor (An article titled “IBM Re-Architects The Mainframe With New Telum Processor” by Jim McGregor, et al., published Aug 23, 2021 and attached to this office action.)
Regarding claims 1, 2, 4-5, and 7-9
Applicant argues on page 7 of their remarks ‘However, a virtual L3 cache as described in Cutress would fail to teach or suggest at least "wherein the on-chip memory in the dedicated area accesses each of the plurality of processing units directly and the on-chip memory in the common area shared by at least two of the plurality of processing units accesses the plurality of processing units via a data bus coupled with the system-on-chip," as recited in amended independent claim 1. That is, the Office Action is mapping the L3 cache of Cutress to the "common area shared by at least two(2) of the plurality of processing units." ‘
Examiner respectfully notes that McGregor is recited in the rejection above to teach the newly amended limitations “wherein the on-chip memory in the dedicated area accesses each of the plurality of processing units directly and the on-chip memory in the common area shared by at least two of the plurality of processing units accesses the plurality of processing units via a data bus coupled with the system-on-chip”. Examiner notes that the claim does not recite all of the on-chip memory is accessed by all of the plurality of processing units directly. The claim recites the limitation that all of the on-chip memory is accessed by the plurality of units directly.
The claim allows for the condition that the “on-chip memory in the dedicated area” may have a subset of the dedicated area allocated to each processing units and each processing unit accesses its portion of the dedicated area directly. This is taught by McGregor as detailed above, as each core of the IBM Telum module directly accesses it’s dedicated memory and may access other cores using a bi-directional ring bus.
Applicant argues on page 7 of their remarks ‘However, the L3 cache of Cutress would fail to teach or suggest "the on-chip memory in the common area shared by at least two of the plurality of processing units accesses the plurality of processing units via a data bus coupled with the system-on-chip." In that, Cutress would fail to teach the physical structure of claim 1 since the L3 cache in Cutress is a virtual cache rather than a physical shared L3 cache.’
Examiner respectfully disagrees. The cache of Cutress is physical cache data. It is a portion of the L2 cache of Cutress that may be shared. In such, it is referred to as a ‘virtual L3’ cache. However that does not change the fact that it is a physical cache and has a physical structure that meets the limitations of claim 1 that requires “on-chip memory comprising .. a common area shared by at least two(2) of the plurality of processing units”. The L2 cache that is shared cache with other CPUs is a common area shared by at least two (2) of the plurality of processing units as claimed.
Applicant’s arguments with respect to dependent claims 2, 4-5, and 7-9 all rely upon perceived errors in claim 1 above and thus have been addressed in the response to remarks in claim 1 above.
Regarding claims 3, 6, and 10-20
Applicant’s arguments with respect to claims 3, 6, and 10-20 all rely upon similar arguments to Applicant’s argument with respect to claim 1 above have been addressed in the response to remarks directed to claim 1 above. Applicant’s remarks that Labbe does not cure the deficiencies of Cutress is moot given McGregor teaches the newly amended limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138
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