DETAILED ACTION
Claims 1 – 24 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/12/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 24 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 - 24 of U.S. Patent No. 12,248,788 in view of Chirca et al (US 2020/0119753, hereinafter referred to as Chirca).
Comparing claim 1 of the instant application to claim 17 of the ‘788 patent, both describe a processing system with a plurality of processors each with a respective local memory block, and enabling each of the processors to access each other processors local memory blocks (the examiner is interpreting the local memory blocks as equivalent to the claimed L1 cache memory of claim 1 of the instant application).
The ’788 patent does not specifically disclose an L2 memory configured to connect to an external memory system, and that each of the processors has access to the L2 cache memory.
However, Chirca teaches an L2 memory configured to connect to an external memory system, and that each of the processors has access to the L2 cache memory (Chirca: figure 1 and paragraph [0053], multi-core shared memory controller 110 with internal shared memory 112, connected to an external memory 114), in order to manage traffic between multiple processor cores and allowing processors to dynamically share the internal and external memories for program instruction and data (Chirca: Paragraph [0053]).
It would have been obvious to one of ordinary skill in the art at the time of filing for the ‘788 patent to implement the L2 memory configured to connect to an external memory system, and that each of the processors has access to the L2 cache memory as taught by Chirca in order to manage traffic between multiple processor cores and allowing processors to dynamically share the internal and external memories for program instruction and data (Chirca: Paragraph [0053]).
Independent claim 13 of the instant application contains similar limitations to claim 1 and is rejected for at least the reasons set forth above. Dependent claims 2 – 12 and 14 – 24 are rejected for at least their dependence upon rejected independent claims above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fan et al (US 2020/0004692) teaches a plurality of processors, each with an independent L1 cache and a shared L2 cache. Fernando (US 2017/0286329) teaches a plurality of processors with individual L1 caches, and the respective L1 caches being connected to one or more shared L2 caches.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZACHARY K HUSON whose telephone number is (571)270-3430. The examiner can normally be reached Monday - Friday 7:00 - 3:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZACHARY K HUSON/Primary Examiner, Art Unit 2181
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