Prosecution Insights
Last updated: October 01, 2026
Application No. 19/042,666

LOW POWER PHASE DETECTION

Non-Final OA §102§103
Filed
Jan 31, 2025
Examiner
JEAN PIERRE, PEGUY
Art Unit
2845
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Components Industries LLC
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
990 granted / 1050 resolved
+26.3% vs TC avg
Minimal -1% lift
Without
With
+-0.8%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
16 currently pending
Career history
1058
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
40.5%
+0.5% vs TC avg
§102
37.9%
-2.1% vs TC avg
§112
10.1%
-29.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1050 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS) submitted on 4/1/26 and 1/22/26 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Garg (US 6,862,315) in view of Birgenheier (US 5,817,719). With regard to claim 1 Garg discloses: A phase detector comprising: an analog to digital converter configured to convert an analog receive signal into a digital receive signal using a sampling clock with a clock frequency equal to at least four times a carrier frequency (para 6: The A/D converter 34 samples the modulated carrier at a clock frequency at least four times that of the carrier frequency to generate a series of sample values); a downconverter configured to convert the digital receive signal into a quadrature baseband signal having an in-phase component and a quadrature phase component; (the digital carrier signal is coupled to a complex mixer 36 which operates to mix down the carrier signal to a base band and generate each of an in-phase (I) and a quadrature phase (Q) base band signal on lines 38(I) and 38(Q) respectively). Garg fails to teach: and an arctangent module configured to derive a phase signal from the quadrature baseband signal. Birgenheier teaches: The signal phase trajectory is provided by calculating the arctangent of the quadrature signals. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to use an arctangent function as taught by Birgenheier for the benefit to obtain the precise angle and trajectory of the signal. With regard to claim 2, Garg discloses: 2. The phase detector of claim 1, wherein the sampling clock is derived from a carrier signal, and wherein the phase signal indicates a phase of the analog receive signal relative to the carrier signal (the A/D converter 34 is a 10-bit A/D converter driven by a 32 MHz clock such that the digital carrier signal is a sequence of 10 bit sample values occurring at a 32 MHz sampling rate). With regard to claim 3, Garg discloses: 3. The phase detector of claim 2, wherein the carrier signal is shared with a transmit signal generator (. network receiver is configured for receiving a modulated carrier signal representing a data frame from a network transmitter via a network medium). With regard to claim 4, Garg and Birgenheier fail to teach: 4. The phase detector of claim 1, wherein the arctangent module includes a look-up table to convert a ratio of the quadrature phase component and in-phase component to a phase angle. the inverse trigonometric functions (occasionally also called antitrigonometric,[1] cyclometric,[2] or arcus functions[3]) are the inverse functions of the trigonometric functions, under suitably restricted domains. Specifically, they are the inverses of the sine, cosine, tangent, cotangent, secant, and cosecant functions,[4] and are used to obtain an angle from any of the angle's trigonometric ratios. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Garg (US 6,862,315). A phase detection method comprising: converting an analog receive signal into a digital receive signal using a sampling clock with a clock frequency equal to at least four times a carrier frequency (para 6: The A/D converter 34 samples the modulated carrier at a clock frequency at least four times that of the carrier frequency to generate a series of sample values); downconverting the digital receive signal into a quadrature baseband signal having an in-phase component and a quadrature phase component; and deriving a phase signal from the in-phase component and the quadrature phase component; (the digital carrier signal is coupled to a complex mixer 36 which operates to mix down the carrier signal to a base band and generate each of an in-phase (I) and a quadrature phase (Q) base band signal on lines 38(I) and 38(Q) respectively). Allowable Subject Matter Claims 5-7, 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 17-20 are allowed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105. /PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845
Read full office action

Prosecution Timeline

Jan 31, 2025
Application Filed
Aug 20, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12738951
INTEGRATED CIRCUIT COMPRISING A DIGITAL-TO-ANALOG CONVERTER
2y 9m to grant Granted Sep 15, 2026
Patent 12736991
Controller for an electronically controlled resistor
2y 10m to grant Granted Sep 15, 2026
Patent 12738958
ENCODING METHOD, DECODING METHOD, APPARATUS, DEVICE, SYSTEM, AND READABLE STORAGE MEDIUM
2y 2m to grant Granted Sep 15, 2026
Patent 12732765
SYSTEM AND METHOD FOR DETECTING ANALOG SIGNALS ON AN AMPLIFIER INPUT AND GATING THE SAME
3y 9m to grant Granted Sep 08, 2026
Patent 12732204
Motor Voltage Reconstruction By ADC Oversampling And Averaging
2y 4m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
94%
With Interview (-0.8%)
1y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1050 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month