DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification Objections
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract of the disclosure is objected to because its length is greater than 150 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
Claims 1 and 8 are objected to because of the following informalities:
Claim 1: Change to “1. A method for failure analysis of a solid-state drive based on a PCIe interface, comprising:…”
Claim 1: Spell out the acronym “PCIe.”
Claim 1: Change to “…designated address in [[a]] the solid-state drive;…”
Claim 8: Change to “8. A solid-state drive comprising a controller, the controller [[is]] configured to[[;]]:”
Claim 8: Change to “…write fault information to a second designated address in batches and update…”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the content in the status register" in page 1. There is insufficient antecedent basis for this limitation in the claim.
Allowable Subject Matter
Claim 3 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 1, 2, and 4-8 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The elements of independent Claims 1 and 8 were neither found through a search of the prior art nor considered obvious by the Examiner. In particular, the prior art of record does not teach or suggest, in combination with the remaining limitations and in the context of their claims as a whole:
Claim 1: “…in response to the first designated address having the predetermined flag, writing, by the controller, fault information to a second designated address in batches and updating an offset address of corresponding content in a third designated address in the fault information with each write to the second designated address, and then clearing the content in the first designated address;…”
Claim 8: “…in response to the first designated address having the predetermined flag, writing fault information to a second designated address in batches and updating an offset address of corresponding content in a third designated address in the fault information with each write to the second designated address, and then clear the content in the first designated address;…”
From a search of the prior art, one reference was found and considered by the Examiner to be the most-related prior art with regards to the claimed invention of the instant application:
Jain et al. (U.S. Patent Application Publication No. US 2023/0195552 A1), hereinafter “Jain.”
Jain: Fig. 3 and Jain: ¶ 0057-0058 teach that a computing endpoint establishes a base address register (BAR) that includes information for translating information between a host system and the computing endpoint. For example, generating and updating a memory register may involve receiving an address from the host system indicating that communications originating from the address (e.g., the source address) may be routed (e.g., via an address translation unit positioned behind the BAR) should be directed to the set aside portion of memory.
In one or more embodiments, the memory register refers to a discoverable resource on the computing endpoint. In particular, the host system may determine how to access one or more values of the memory register without requiring that the computing endpoint expressly communicate data to the host system. In one or more embodiments, the memory register may include a discoverable value or indicator to indicate whether a failure condition exists. For instance, the discoverable value may include a flag or other indicator that a crash dump has occurred or that the computing endpoint is uncertain about one or more sub-systems operating correctly. As mentioned above, the host system can access the discoverable value without the computing endpoint transmitting or otherwise providing data over a communication link.
Although conceptually similar to the claimed invention of the instant application, Jain does not teach, in response to the first designated address having the predetermined flag, writing fault information to a second designated address in batches and updating an offset address of corresponding content in a third designated address in the fault information with each write to the second designated address, and then clear the content in the first designated address.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Jain (see above).
Plum et al. (U.S. Patent No. US 11,880,291 B2); teaching monitoring and reporting a status of a memory device. A memory device may include monitoring circuitry that may be configured to monitor health and wear information for the memory device. A host device may write to a dedicated register of the memory device, to configure the memory device with health status information reporting parameters. The memory device may monitor and report the health status information of the memory device based on the received reporting configuration or based on a default configuration, and may write one or more values indicative of the health status information to a dedicated register. The host device may perform a read on the readout register to obtain the health status information, as indicated by the one or more values, and may adjust operating procedures or take other actions based on the received health status information.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH KUDIRKA whose telephone number is (571)270-7126. The examiner can normally be reached M-F 7:30am - 5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at (571) 272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSEPH R KUDIRKA/Primary Patent Examiner, Art Unit 2114