DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/03/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Vertical Hall element capable of adjusting magnetic detection sensitivity.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over SEKIGUCHI (US PGPUB 2023/0403950) in view of MOZSÁRY et al. (US PGPUB 2016/0018475).
Regarding claim 1, SEKIGUCHI teaches a vertical Hall element, comprising: a semiconductor substrate (30), having a first conductivity type (as shown in fig. 4 and disclosed in para. 0040); an impurity diffusion layer (30c), having a second conductivity type and formed on a surface of the semiconductor substrate (30) (as shown in fig. 4 and disclosed in para. 0041); an electrode group (51, 52, 55 and 71-73, as shown in fig. 4), disposed on a surface of the impurity diffusion layer (top surface, as shown in fig. 4), wherein three or more electrodes (51, 52, 55 and 71-73) are disposed linearly (as shown in fig. 4); a constant current source (21), causing a constant current to flow among the electrodes of the electrode group (51, 52, 55 and 71-73) (as shown in fig. 1 and disclosed in para. 0037).
SEKIGUCHI fails to specifically teach a first conductor, disposed to be overlapped with at least a portion of the current path of the constant current when viewed in a plan view, and able to be applied with a predetermined voltage. However, MOZSÁRY et al. teaches a first conductor (CWA), disposed to be overlapped with at least a portion of the current path of the constant current (I1a or I1b) when viewed in a plan view (as shown in fig. 1 and 3B), and able to be applied with a predetermined voltage (as discussed in para. 0060).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the first conductor, disposed to be overlapped with at least a portion of the current path of the constant current when viewed in a plan view, and able to be applied with a predetermined voltage as taught by MOZSÁRY et al. with the invention of SEKIGUCHI in order to have sensor values with a higher significance due to the higher magnetic field intensity (MOZSÁRY et al. para. 0060).
Regarding claim 2, the combination of SEKIGUCHI and MOZSÁRY et al. teaches the limitations of claim 1, in addition, MOZSÁRY et al. teaches wherein the first conductor (CWA) is disposed above the electrode group (A-D) (as shown in fig. 1 and 3B).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the first conductor disposed above the electrode group as taught by MOZSÁRY et al. with the invention of SEKIGUCHI in order to increase the magnetic field intensity generated (MOZSÁRY et al. para. 0060).
Regarding claim 3, the combination of SEKIGUCHI and MOZSÁRY et al. teaches the limitations of claim 2, in addition, MOZSÁRY et al. teaches wherein the first conductor (CWA) is a metal layer (as disclosed in para. 0055) or a high-concentration impurity conductor formed by polysilicon.
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over SEKIGUCHI (US PGPUB 2023/0403950) and MOZSÁRY et al. (US PGPUB 2016/0018475) as applied to claim 1 above, and further in view of HEBERT (US PGPUB 2016/0018478).
Regarding claim 6, the combination of SEKIGUCHI and MOZSÁRY et al. teaches the limitations of claim 1, in addition, SEKIGUCHI teaches wherein the first conductivity type is P- type (as disclosed in para. 0040), and the second conductivity type is N-type (as disclosed in para. 0041).
The combination of SEKIGUCHI and MOZSÁRY et al. fails to specifically teach wherein the electrode group is formed by using a P-type high-concentration impurity conductor formed of polysilicon. However, HEBERT teaches wherein the electrode group (130, 230 and 430) is formed by using a P-type high-concentration impurity conductor formed of polysilicon (as disclosed in para. 0090).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the electrode group formed by using a P-type high-concentration impurity conductor formed of polysilicon as taught by HEBERT with the invention of the combination of SEKIGUCHI and MOZSÁRY et al. in order to have low resistivity (HEBERT para. 0090).
Allowable Subject Matter
Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the prior art fails to specifically teach a vertical hall element, comprising: wherein the first conductor is a buried layer having the first conductivity type and disposed below the electrode group.
Regarding claim 5, the prior art fails to specifically teach a vertical hall element, comprising: a second conductor disposed to be overlapped with at least a portion of the current path of the constant current when viewed in a cross-sectional view and formed by polysilicon having the first conductivity type, in combination with all the limitations of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERTO VELEZ whose telephone number is (571)272-8597. The examiner can normally be reached Mon-Fri 5:30am-3:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ROBERTO VELEZ/Primary Examiner, Art Unit 2858
Prosecution Insights