Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under U.S.C. 103 as being unpatentable over Wang et al. (US Pat. Pub. 20250055480; filed 08/10/2023; hereinafter referred to as Wang) in view of Alhussien et al. (US Pat. Pub. 20170236592; hereinafter referred to as Alhussien).
As per claims 1, 8, and 15:
Wang teaches a system (Wang par. 0017, system 100), method (Wang par. 0109, method), and non-transitory computer-readable storage medium (Wang par. 0094, non-transitory computer-readable storage medium 808) comprising
a memory device (Wang par. 0017, storage system 115); and
a processing device (Wang par. 0094, controller 804), operatively coupled to the memory device, the processing device to:
read, from the memory device, at a current stage of a read error handling sequence, current stage data representing a subset of encoded data stored in a plurality of memory cells of the memory device (Wang par. 0036, perform current read operations for assist read zone 0 corresponding to various read threshold voltages for reading contents of memory cells. Please note the read operations are performed on a set of encoded memory cells as stated in Wang par. 0018);
determine, for each decoder input bin of a plurality of decoder input bins, a first number of memory cells having their respective threshold voltages falling into the decoder input bin and further having a first binary value (Wang par. 0046, determine a first set of counters for each bin with a first binary value. Please note the counters track memory cells and their respective threshold voltages as stated in Wang par. 0036 and 0048);
determine, for each decoder input bin of the plurality of decoder input bins, a second number of memory cells having their respective threshold voltages falling into the decoder input bin and further having a second binary value (Wang par. 0046, determine a second set of counters for each bin with a second binary value. Please note the counters track memory cells and their respective threshold voltages as stated in Wang par. 0036 and 0048)
calibrate, for each decoder input bin of the plurality of decoder input bins, a corresponding likelihood value based on the first number of memory cells associated with the decoder input bin and the second number of memory cells associated with the decoder input bin (Wang par. 0087, calibrate corresponding LLR values for bins in each AR zone);
associate each memory cell of the plurality of memory cells with a respective likelihood value corresponding to a decoder input bin comprising a threshold voltage exhibited by the memory cell (Wang par. 0036-0037, associate memory cells with respective LLR values to a bin according to read threshold voltages); and
decode, based on a plurality of likelihood values associated with the plurality of memory cells, the current stage data (Wang par. 0089-0090, error correction decoding is performed on the data stored in the multibit memory cells based on LLR values).
Wang does not explicitly disclose a first binary value yielded by a previous stage of the read error handling sequence and a second binary value yielded by a previous stage of the read error handling sequence. However, Alhussien discloses a first binary value yielded by a previous stage of the read error handling sequence and a second binary value yielded by a previous stage of the read error handling sequence (Alhussien par. 0109, syndrome weights of previous read retry operations are used to select a LLR assignment. Please note the likelihood values indicate a first and second binary value as stated in Alhussien par. 0019).
Wang and Alhussien are analogous arts because they are in the same field of endeavor of error correction. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Alhussien’s binary values yielded by a previous stage of read error handling sequences with the system, method, and non-transitory computer-readable storage medium of Wang. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it allows for the optimal reference voltage to be used as the starting point in future read retry operations (Alhussien par. 0021).
As per claims 2, 9, and 16:
Wang and Alhussien further teach the system of claim 1, method of claim 8, and non-transitory computer-readable storage medium of claim 15, wherein a likelihood value associated with a particular decoder input bin reflects a probability of a memory cell having its threshold voltage within the particular bin to be decoded as a particular binary value (Wang par. 0036-0039, probability of LLR values of different bins having its threshold voltage being decoded as a particular binary value).
As per claims 3, 10, and 17:
Wang and Alhussien further teach the system of claim 1, method of claim 8, and non-transitory computer-readable storage medium of claim 15, wherein the likelihood value associated with a decoder input bin is a logarithm of the ratio of the first number of memory cells having the first binary value yielded by the previous stage of the read error handling sequence and the second number of memory cells having the second binary value yielded by the previous stage of the read error handling sequence (Wang par. 0087-0088, LLR values associated with a bin is a logarithm of a ratio of a first set of counters and a second set of counters having binary values).
As per claims 4, 11, and 18:
Wang and Alhussien further teach the system of claim 1, method of claim 8, and non-transitory computer-readable storage medium of claim 15, wherein the previous stage read of the error handling sequence exhibits a smallest syndrome weight among syndrome weights of a plurality of stages preceding the current stage in the read error handling sequence (Alhussien par. 0095-0098, previous read retry operations exhibit a minimum syndrome weight).
As per claims 5, 12, and 19:
Wang and Alhussien further teach the system of claim 1, method of claim 8, and non-transitory computer-readable storage medium of claim 15, wherein decoding the current stage data is performed using a low-density parity-check (LDPC) matrix (Wang par. 0021, LDPC decoder uses a decoder parity-check matrix).
As per claims 6, 13, and 20:
Wang and Alhussien further teach the system of claim 1, method of claim 8, and non-transitory computer-readable storage medium of claim 15, wherein calibrating, for each decoder input bin of the plurality of decoder input bins, a corresponding likelihood value (Wang par. 0087) is performed responsive to determining that a syndrome weight produced by the previous stage falls below a threshold syndrome weight value (Alhussien par. 0095, use the lowest syndrome weight to select likelihood value assignments for future retry operations. Please note the lowest syndrome weight is a past minimum syndrome weight as stated in Alhussien par. 0101).
As per claims 7 and 14:
Wang and Alhussien further teach the system of claim 1, method of claim 8, and non-transitory computer-readable storage medium of claim 15, wherein the processing device is further to: responsive to determining that a codeword produced by decoding the current stage data comprises one or more errors, performing a next stage of the read error handling sequence (Alhussien par. 0096-0097, if decoding is not a success, perform a next read retry operation).
Conclusion
The additional prior arts made of record and have not been relied upon are considered pertinent to applicant’s disclosure as follows:
Chen et al. (US Pat. Pub. 20190378576) discloses methods and systems related to a sequence of read level voltages for decoding operations based on a first decoding success indicator and a second decoding success indicator. Chen further discloses confidence values assigned to bins for soft-decoding operations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A YANG whose telephone number is (703)756-1447. The examiner can normally be reached Monday - Friday 8:30 a.m. - 5:30 p.m. EST.
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/JEFFREY ANDREW YANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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