DETAILED ACTION
This action is responsive to the preliminary amendment filed on 5/23/2025. Claim 1 has been cancelled. Claims 2-21 have been added. Claims 2-21 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Claim 21 recites the following contingent limitations: “…and disabling, based on the sampling parameter and by the computational array, particular computational units of the computational array when performing the portion of computation processing”
The contingent limitations use the language “when” and are contingent because they precede steps that are only required to be performed when (i.e. if) a condition is met. For example, the steps of “disabling particular computational units” are only required to be performed when (e.g. “if”) the portion of computation processing is performed. However, if the portion of computation processing is not being performed (e.g. another or second portion of processing is occurring) the steps of “disabling particular computational units” are not required to occur based on the broadest reasonable interpretation given to contingent limitations in method claims (See MPEP 2111.04(II) See Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016)).
The examiner suggests amending the claim to remove the contingent limitations stating “when” and to positively recite each step of the method claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2 and 4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6 and 8-9 of U.S. Patent No. 11,681,649. Although the claims at issue are not identical, they are not patentably distinct from each other because each of the above claims of the instant application is an obvious variant of a corresponding claim of U.S Patent No. 11,681,649.
Claims 2 and 4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 15 and 17-18 of U.S. Patent No. 11,157,441. Although the claims at issue are not identical, they are not patentably distinct from each other because each of the above claims of the instant application is an obvious variant of a corresponding claim of U.S Patent No. 11,157,441.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 4, the limitations stating “The microprocessor system of claim 2, wherein the sampling parameter comprises a kernel size, a step size, a down-sampling factor, a stride, or a spatial extent associated with the computational array” lacks clarity or is indefinite because the claim is inconsistent with the specification disclosure (See MPEP 2173.03). The examiner notes that claim 4 is dependent upon claim 2, which states “hardware data formatter configured to (i) provide, based on a sampling parameter, a first portion of the group of values to the computational array …wherein the computational array disables particular computational units based on the sampling parameter”, thus the sampling parameters listed in claim 4 would need to be used to provide data values and disable computational units. However, the specification has not described using any other parameter, outside of a stride value, to provide values and disable computational units (see paragraph [0087]). Rather, paragraph [0039] discloses pooling parameters used for pooling operations that include kernel size, stride, and/or spatial extent; but this operation is not used in the providing of values nor disabling of computational units disclosed in paragraph [0087]. Thus, the claim is unclear because it appears to be inconsistent with the details disclosed in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 5, 7-8, 11-12 and 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over NPL reference “Re-architecting the On-chip memory Sub-system of Machine-Learning Accelerator for Embedded Devices” hereby referred to as Wang, and further in view of Sebexen, PGPUB No. 2018/0107484 (cited on IDS filed on 7/29/2025).
In regards to claim 2, Wang discloses A microprocessor system (See Fig. 1 on page 2) comprising: a computational array that includes a plurality of computation units (see page 2, section 3.1: wherein the CNN accelerator includes an array of processing elements (PEs) (also see Fig. 1)) wherein an individual computation unit operates on a corresponding value of a group of values addressed from memory (see page 2, section 3.1 and page 5, section 3.5: wherein each PE operates on corresponding input data values of a group of values addressed from memory (see Fig. 1)) and a hardware data formatter configured to (i) provide, based on a sampling parameter, a first portion of the group of values to the computational array for a first computation processing (see page 2, section 3.1: wherein combination of AGU and active buffer is interpreted to be a hardware data formatter to provide a first portion of the group of values to the array of PEs for a first computation processing of a convolution layer, based on a redundancy parameter (sampling parameter) (“The AGUs generates the continuous address offsets to the index buffers, and drive they to finally produce the uncompressed weight and data for the high throughput PEs”). See pages 4-5, section 3.4: “Even when the current issue windows cannot be skipped due to the existence of non-zero input words, the mask signals can also be sent to AGUs to prevent loading the zero-data from either data or weight buffer, so that only the unmasked data-weight pairs are received by the according PEs while the other PEs are disabled, which is to save energy by disabling the unnecessary data load and computation.” Wherein AGU’s use a redundancy mask/signal (e.g. parameter) to provide a sample of values to the PE’s which excludes zero values (also see Fig. 1)) and (ii) perform a buffer check to obtain the first portion of the group of values (see page 2, section 3.1: wherein AGU performs a check in active buffer to obtain the first portion of the group of values (“The AGUs generates the continuous address offsets to the index buffers, and drive they to finally produce the uncompressed weight and data for the high throughput PEs”). See page 2, section 3.1: “Therefore, Memsqueezer is to provide an active on-chip memory subsystem with a higher capacity and bandwidth utility so that both weight and data can be handled in low overhead CNN accelerators without inducing frequent buffer misses”. Thus, the buffer is checked to determine if a miss or hit occurs) wherein the computational array disables particular computational units based on the sampling parameter. (See pages 4-5, section 3.4: “Even when the current issue windows cannot be skipped due to the existence of non-zero input words, the mask signals can also be sent to AGUs to prevent loading the zero-data from either data or weight buffer, so that only the unmasked data-weight pairs are received by the according PEs while the other PEs are disabled, which is to save energy by disabling the unnecessary data load and computation.” Wherein PEs are disabled based on the redundancy mask/signal (sampling parameter))
Wang does not explicitly disclose perform a cache check to obtain the first portion of the group of values. While, Wang discloses performing a check of a buffer memory to determine if values needed for the CNN accelerator are located on-chip, Wang does not disclose checking a cache memory.
Sebexen discloses perform a cache check to obtain data ([0024-0025]: wherein a cache is checked to obtained data)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the checking of a buffer structure of Wang to include a checking of a cache structure as taught in Sebexen. It would have been obvious to one of ordinary skill in the art because it would have been simple substitution of one known element (using a cache memory to store data as taught in Sebexen) for another (using a generic buffer structure to store data as taught in Wang) to obtain predictable results (checking an on-chip cache data structure to obtain data values) (MPEP 2143, Example B). Furthermore, using a cache memory can store copies of frequently used data from main memory and result in future requests for data being served faster (Sebexen [0024-0025]).
Claim 21 is the method claim corresponding to the system of claim 2 above, and therefore is similarly rejected on the same basis as claim 2 above.
In regards to claim 3, the combination of Wang and Sebexen discloses The microprocessor system of claim 2 (see rejection of claim 2) wherein the sampling parameter corresponds to an architecture of a machine learning model associated with the computational array. (Wang: see pages 2 and 4-5, sections 3.1 and 3.4: wherein a redundancy mask/signal (sampling parameter) corresponds to an architecture of a CNN associated with the array of Fig. 1)
In regards to claim 5, the combination of Wang and Sebexen discloses The microprocessor system of claim 2 (see rejection of claim 2) wherein a computation unit of the plurality of computation units is configured to perform at least a dot-product component operation using the group of values in parallel. (Wang: pages 2-3, sections 2 and 3.1: “Early CNN accelerators are focused on datapath optimization. [2] exploits data-level parallelism…processing elements (PEs) that carry out multiply and-accumulate and other arithmetic operations… The AGUs generates the continuous address offsets to the index buffers, and drive they to finally produce the uncompressed weight and data for the high throughput PEs.” Wherein a PE performs a multiply accumulate operation which is a component of a dot-product operation and thus is a dot product component operation using the group of values in parallel with other PEs)
In regards to claim 7, the combination of Wang and Sebexen discloses The microprocessor system of claim 2 (see rejection of claim 2 above) wherein a computation unit of the plurality of computation units includes an accumulator (Wang: page 2, Fig. 1: wherein each PE includes an accumulator (combination of adders))
The combination of Wang and Sebexen thus far does not disclose wherein a computation unit of the plurality of computation units includes an arithmetic logic unit and a shadow register.
Sebexen discloses wherein a core of the plurality of cores includes an arithmetic logic unit and a shadow register. ([0023]: wherein a core includes an ALU and a register file)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the PEs of Wang to include an ALU and a register as disclosed in the cores of Sebexen. It would have been obvious to one of ordinary skill in the art because it be the simple substitution of one known element (using an ALU to perform arithmetic operations including multiplications as taught in Sebexen) for another (using a multiplier to perform multiplications as taught in Wang) to yield predictable results (using ALUs to perform multiplication operations and other arithmetic operations) (MPEP 2143, Example B). It would have been further obvious to include a register in the PEs as to allow them to have local memories to store data, using fast and efficient register storage.
In regards to claim 8, the combination of Wang and Sebexen discloses The microprocessor system of claim 2 (see rejection of claim 2) wherein the group of values corresponds to an input channel of vision data or sensor data. (Wang: see page 1: “Deep convolutional neural networks (CNN) are making substantial
progress in computer vision, image processing, speech recognition and
other Recognition, Mining and Synthesis (RMS) applications”. Page 5 “The input test dataset is from the ImageNet validation set [13 ]. The accelerators will execute the inference procedure of different CNNs that are to classify these random ImageNet pictures.” Wherein input values for CNN accelerator of Fig. 1 on page 2 corresponds to an input channel of vision or image data.)
In regards to claim 11, the combination of Wang and Sebexen discloses The microprocessor system of claim 2 (see rejection of claim 2) wherein the group of values corresponds to a convolution filter. (Wang: page 2, sections 2-3.1: “Deep convolutional neural networks relates to intensive convolution operations between a bunch of feature maps (data) and pre-trained kernel filters (weight)… fetch both weight and data into PEs. Except hardware, a compiler is often required to translate the network specification, including the information like
layer count, layer type, kernels size, kernel count and active-function…”)
In regards to claim 12, the combination of Wang and Sebexen discloses The microprocessor system of claim 11 (see rejection of claim 11) wherein the convolution filter is constructed to identify features of an input data. (Wang: page 2, sections 2-3.1: “Deep convolutional neural networks relates to intensive convolution operations between a bunch of feature maps (data) and pre-trained kernel filters (weight)… fetch both weight and data into PEs. Except hardware, a compiler is often required to translate the network specification, including the information like layer count, layer type, kernels size, kernel count and active-function…In addition to the weight buffer set, the data buffers are used to store the feature data and the intermediate data, which is produced by one CNN layer and then consumed by the next layer in a streaming way.” Wherein a weight (kernel filter) identifies features in input data)
In regards to claim 19, the combination of Wang and Sebexen discloses The microprocessor system of claim 2 (see rejection of claim 2 above) wherein the cache check is performed for the first portion of the group of values based on determining whether a first value and a last value for the first portion of the group of values are stored in a cache. (Sebexen [0024-0025]: wherein a cache is checked to obtain data (Note: Wang pages 2 and 5, sections 3.1 and 3.5: discloses streaming the portion of data which would include a first and last value and thus the cache check would be determining whether the required first and last value are located in the cache or buffer. Thus, the combination of references discloses the above limitation))
In regards to claim 20, the combination of Wang and Sebexen discloses The microprocessor system of claim 2 (see rejection of claim 2) wherein the first portion of the group of values are synchronously provided together to the computational array to be processed in parallel in the first computation processing. (Wang: pages 2-3: “… Early CNN accelerators are focused on datapath optimization. [2] exploits data-level parallelism… In addition to the weight buffer set, the data buffers are used to store the feature data and the intermediate data, which is produced by one CNN layer and then consumed by the next layer in a streaming way…The AGUs generates the continuous address offsets to the index buffers, and drive they to finally produce the uncompressed weight and data for the high throughput PEs…”. See page 5, section 3.5: “In Memsqueezer, the weight and data are continuously streamed out of buffers to PEs in deterministic time steps under the control of AGUs.” Wherein the first portion of values are synchronously provided to the array of PEs to be processed in parallel for a first convolution layer processing)
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang, Sebexen and further in view of Nariyambut, PGPUB No. 2017/0206434 (cited on IDS filed on 7/29/2025).
In regards to claim 6, the combination of Wang and Sebexen discloses The microprocessor system of claim 2 (see rejection of claim 2) computational array (Wang: see page 2, Fig. 1: array of PEs)
The combination of Wang and Sebexen does not disclose wherein an output of the computational array includes a scalar value. Wang does disclose a CNN accelerator including a computational array used to generate an output. However, Wang does not disclose a convolutional accelerator generating a scalar output.
Nariyambut discloses wherein an output of the computational accelerator includes a scalar value ([0035 and 0039]: wherein an output of a GPU performing CNN operations includes a scalar value output)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the output of the CNN accelerator of Wang to include a scalar value as the output of the CNN processor of Nariyambut. It would have been obvious to one of ordinary skill in the art because it be the simple substitution of one known element (generating a scalar output for a CNN accelerator as taught in Nariyambut) for another (generating a generic output for a CNN accelerator as taught in Wang) to yield predictable results (generating a scalar output for a CNN accelerator) (MPEP 2143, Example B).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang, Sebexen and further in view of Young, PGPUB No. 2016/0342890 (cited on IDS filed on 7/29/2025).
In regards to claim 9, the combination of Wang and Sebexen discloses The microprocessor system of claim 8 (see rejection of claim 8 above).
The combination of Wang and Sebexen does not explicitly disclose wherein the sensor data is non-image sensor data. Wang does generally disclose using convolution neural networks used for speech recognition, but does not explicitly disclose non-image sensor data.
Young discloses wherein the sensor data is non-image sensor data. ([0046 and 0074]: wherein input data consist of audio sensor data)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the input data of the CNN accelerator of Wang to include audio sensor data as the neural networking processor of Young. It would have been obvious to one of ordinary skill in the art because it be the simple substitution of one known element (using audio input data in a neural networking processor as taught in Young) for another (using input data in a CNN processor as taught in Wang) to yield predictable results (using audio sensor data for neural network processing as to perform applications such as speech recognition) (MPEP 2143, Example B).
In regards to claim 10, the combination of Wang, Sebexen and Young discloses The microprocessor system of claim 9 (see rejection of claim 9 above) wherein the first portion is retrieved from a cache using a single cache read. (Sebexen [0025]: wherein data is accessed from cache in a single cache read if a hit in the cache occurs (note: Wang discloses the first portion of data and the combination of references discloses the above limitation))
Allowable Subject Matter
Claim 4 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112 and double patenting, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious claim 4 filed on 5/23/2025. The prior art of record has not taught either individually or in combination and together with all other claimed features “The microprocessor system of claim 2, wherein the sampling parameter comprises a kernel size, a step size, a down-sampling factor, a stride, or a spatial extent associated with the computational array.”
The closest prior art of record, Wang discloses using a sampling redundancy parameter to disable PEs and provide values to the computational array. However, Wang does not disclose “…the sampling parameter comprising a kernel size, a step size, a down-sampling factor, a stride, or a spatial extent associated with the computational array” as claimed in claim 4.
Furthermore, while some limitations may be broadly disclosed in the references above and in the pertinent art section below, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious claim 13 filed on 5/23/2025. The prior art of record has not taught either individually or in combination and together with all other claimed features “The microprocessor system of claim 2, wherein the hardware data formatter is further configured to (i) identify a second portion of the group of values not provided for the first computation processing, and (ii) provide the second portion of the group of values to the computational array for a second computation processing subsequent to the first computation processing.”
The closest prior art of record, Wang discloses using a hardware data formatter to identify intermediate data values generated by the first computation processing of a first convolutional layer and provides the intermediate data to a subsequent computation processing of a second convolutional layer. However, Wang does not disclose “The microprocessor system of claim 2, wherein the hardware data formatter is further configured to (i) identify a second portion of the group of values not provided for the first computation processing, and (ii) provide the second portion of the group of values to the computational array for a second computation processing subsequent to the first computation processing” as claimed in claim 13.
Furthermore, while some limitations may be broadly disclosed in the references above and in the pertinent art section below, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Claims 14-18 are dependent upon claim 13 above and therefore are similarly allowable for the same reasons as claim 13 above.
Conclusion
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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