Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner cites particular columns or paragraphs, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0415231), in view of Kang et al. (US 2022/0284855).
Regarding claim 1, Lee discloses a display device (see e.g. display device in Fig. 14; para[0007]; para[0025]; para[0099]) comprising:
a display panel comprising pixels (see e.g. display panel 9000 comprising pixels PX as shown in Fig. 14);
a low-dropout circuit configured to generate an internal power supply voltage, and to provide the internal power supply voltage to the pixels through a power supply line (para[0040]-para[0042]; para[0044]; para[0054]; para[0072]; para[0083]; para[0100]; see in Figs. 2A-3B, 6A-6B and 8, analog low dropout (LDO) regulator 1120/4120 generates a first output voltage of the internal power supply mode (referred to as a “first internal output voltage”) VOUT1_INT having a specific level, which is included in analog power supply voltage AVDD provided through a power line to pixels PX in Fig. 14);
a load switch circuit configured to receive an external power supply voltage, and to selectively provide the external power supply voltage to the power supply line in response to a load switch enable signal (para[0042]; para[0078]; para[0083]-para[0084]; para[0100]; “multiplexer 4400 may receive the first internal input voltage VIN1_INT and the first external input voltage VIN1_EXT”; “The multiplexer 4400 may select one of the first internal input voltage VIN1_INT and the first external input voltage VIN1_EXT based on a multiplexer control signal MCTR”; see in Figs. 2A-2B, 7A-7B and 8, multiplexer 1400/4400 receives a first input voltage of the external power supply mode (hereinafter referred to as a “first external input voltage”) VIN1_EXT from the power management integrated circuit 10, and selectively provides it as VIN1, to be subsequently included in VOUT_EXT, and provided in the analog power supply voltage AVDD to the power line to pixels PX in Fig. 14); and
a controller configured to generate the load switch enable signal (para[0084]; “the multiplexer control signal MCTR may be controlled (or generated) by a separate controller (not illustrated) located inside or outside the power module 4000”; “For example, the controller (not illustrated) may generate the multiplexer control signal MCTR for determining whether a first power module 4100 operates in the internal power supply mode or the external power supply mode, so as to coincide with a power level that the system load 20 requires”).
However, Lee does not appear to expressly disclose the low-dropout circuit configured to generate the internal power supply voltage in response to a low-dropout enable signal; and the controller configured to generate the low-dropout enable signal.
Kang discloses a low-dropout circuit configured to generate an internal power supply voltage in response to a low-dropout enable signal (para[0006]; para[0101]; para[0105]; regarding Figs. 1-2 and 6, “when the timing controller 11 applies a second control signal to the LDO regulator 161′ through the second line ELVDD_EN2, the LDO regulator 161′ may apply a voltage of a second level to the first power line ELVDD”); and a controller configured to generate the low-dropout enable signal (para[0105]; as shown in Fig. 6, timing controller 11 generates the second control signal applied through the second line ELVDD_EN2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Lee’s invention, with the teachings in Kang’s invention, to have the low-dropout circuit configured to generate the internal power supply voltage in response to a low-dropout enable signal; and the controller configured to generate the low-dropout enable signal and the load switch enable signal, for the advantage of a control configuration with which influence of noise may be minimized, and characteristic sensing accuracy of the pixel may be increased (para[0005]; para[0121]-para[0122]).
Regarding claim 5, Lee and Kang disclose all the claim limitations as applied above (see claim 1). In addition, Kang discloses the controller is configured to activate the low-dropout enable signal in a sensing period in which characteristics of pixels are sensed (regarding Figs. 6-7, during “The first period… from a first time point t1a′ to a second time point t2a′”, “the timing controller 11 applies a second control signal to the LDO regulator 161′ through the second line ELVDD_EN2, the LDO regulator 161′ may apply a voltage of a second level to the first power line ELVDD” and “the voltage of the second level may be a second power voltage used in the pixel PXij during the sensing period” in which characteristic of the pixel is sensed; para[0005]; para[0105]; para[0111]-para[0114]; para[0119]; para[0122]), and wherein the low-dropout circuit is configured to provide the internal power supply voltage to a power supply line in response to the activated low-dropout enable signal (para[0105]; regarding Figs. 1-2 and 6-7, “when the timing controller 11 applies a second control signal to the LDO regulator 161′ through the second line ELVDD_EN2, the LDO regulator 161′ may apply a voltage of a second level to the first power line ELVDD”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the controller is configured to activate the low-dropout enable signal in a sensing period in which characteristics of the pixels are sensed, and wherein the low-dropout circuit is configured to provide the internal power supply voltage to the power supply line in response to the activated low-dropout enable signal, for the advantage of a control configuration with which influence of noise may be minimized, and characteristic sensing accuracy of the pixel may be increased (para[0005]; para[0121]-para[0122]).
Regarding claim 6, Lee and Kang disclose all the claim limitations as applied above (see claim 5). In addition, Kang discloses the controller is configured to deactivate the load enable signal in the sensing period, and wherein a load circuit is configured to reduce or block a power supply voltage to the power supply line in response to the deactivated load enable signal (regarding Figs. 6-7, e.g. “when the timing controller 11 applies a first control signal to the buck converter 160′ through the first line ELVDD_EN1, the buck converter 160′ may apply a voltage of a first level to the first power line ELVDD”; however, during “The first period… from a first time point t1a′ to a second time point t2a′”, “the timing controller 11 does not apply the first control signal to the buck converter 160′ through the first line ELVDD_EN1”, thus blocking a supply of the voltage of the first level to the first power line ELVDD in response to the deactivated first control signal through line ELVDD_EN1; para[0103]; para[0111]-para[0113]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the controller is configured to deactivate the load switch enable signal in the sensing period, and wherein the load switch circuit is configured to reduce or block the external power supply voltage to the power supply line in response to the deactivated load switch enable signal, in the combination, for the advantage of only applying a power voltage having lower noise such that the pixel may be stably driven during the sensing period (para[0119]).
Regarding claim 7, Lee and Kang disclose all the claim limitations as applied above (see claim 5). In addition, Kang discloses a sensing circuit connected to the pixels through sensing lines, and configured to sense the characteristics of the pixels in the sensing period (regarding Figs. 1-2, see sensing transistor T3 connected to sensing lines Ik and scan lines S2i, configured to sense characteristic of the pixels PXij when the second power voltage is provided to the first power line ELVDD during the sensing period, such that “the sensing unit 15 may sense unique characteristic values of circuit elements included in the pixel PXij”; para[0062]; para[0071]-para[0073]; para[0081]-para[0082]; para[0119]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have a sensing circuit connected to the pixels through sensing lines, and configured to sense the characteristics of the pixels in the sensing period, for the advantage of a feasible mechanism with which pixel characteristic variation is measured in order to be compensated for (para[0005]).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0415231), in view of Kang et al. (US 2022/0284855), and further in view of Tseng (US 2023/0221745).
Regarding claim 2, Lee and Kang disclose all the claim limitations as applied above (see claim 1). In addition, Kang discloses the controller is configured to activate the low-dropout enable signal in a power-on period of the display device, and wherein the low-dropout circuit is configured to provide the internal power supply voltage to a power supply line in response to the activated low-dropout enable signal(regarding Figs. 6-7, during “The first period… from a first time point t1a′ to a second time point t2a′”, “the timing controller 11 applies the second control signal to the LDO regulator 161′ through the second line ELVDD_EN2”; “In the first period, the LDO regulator 161′ to which the second control signal is applied may apply a voltage of a second level to the first power line ELVDD”; para[0111]-para[0114]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the controller is configured to activate the low-dropout enable signal in a power-on period of the display device, and wherein the low-dropout circuit is configured to provide the internal power supply voltage to the power supply line in response to the activated low-dropout enable signal, for the advantage of applying a power voltage having lower noise such that the pixel may be stably driven during a sensing period (para[0119]).
However, Lee and Kang do not appear to expressly disclose the controller is configured to perform an overcurrent detection operation for determining whether a current flowing through the power supply line is greater than or equal to a reference current.
Tseng discloses performing an overcurrent detection operation for determining whether a current flowing through a power supply line is greater than or equal to a reference current (para[0032]-para[0034]; FIG. 3 is block diagram of a low-dropout voltage regulator system using an overcurrent detection circuit; “The overcurrent circuit 1 (or 1′) is configured to obtain the sensed current Isen and the reference current Iref, and determine whether the output current of the low-dropout regulator 21 is the overcurrent”, that is, if the current Isen in a power line providing voltage VDD is greater than current Iref).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Lee’s and Kang’s combination, with the teachings in Tseng’s invention, to have the controller is configured to perform an overcurrent detection operation for determining whether a current flowing through the power supply line is greater than or equal to a reference current, for the advantage of determining whether output current is too high, and adjust and compensate excessive output current correspondingly, at a low cost and in a simple way (para[0003]; para[0006]).
Regarding claim 3, Lee, Kang and Tseng disclose all the claim limitations as applied above (see claim 2). In addition, Kang discloses the controller is configured to deactivate a load enable signal in the power-on period, and wherein a load circuit is configured to reduce or block a power supply voltage to the power supply line in response to the deactivated load enable signal (regarding Figs. 6-7, e.g. “when the timing controller 11 applies a first control signal to the buck converter 160′ through the first line ELVDD_EN1, the buck converter 160′ may apply a voltage of a first level to the first power line ELVDD”; however, during “The first period… from a first time point t1a′ to a second time point t2a′”, “the timing controller 11 does not apply the first control signal to the buck converter 160′ through the first line ELVDD_EN1”, thus blocking a supply of the voltage of the first level to the first power line ELVDD in response to the deactivated first control signal through line ELVDD_EN1; para[0103]; para[0111]-para[0113]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the controller is configured to deactivate the load switch enable signal in the power-on period, and wherein the load switch circuit is configured to reduce or block the external power supply voltage to the power supply line in response to the deactivated load switch enable signal, in the combination, for the advantage of only applying a power voltage having lower noise such that the pixel may be stably driven during a sensing period (para[0119]).
Regarding claim 4, Lee, Kang and Tseng disclose all the claim limitations as applied above (see claim 2). In addition, Lee discloses wherein the load switch circuit is configured to provide the external power supply voltage to the power supply line in response to the activated load switch enable signal (para[0042]; para[0078]; para[0083]-para[0084]; para[0100]; “multiplexer 4400 may receive the first internal input voltage VIN1_INT and the first external input voltage VIN1_EXT”; “The multiplexer 4400 may select one of the first internal input voltage VIN1_INT and the first external input voltage VIN1_EXT based on a multiplexer control signal MCTR”; see in Figs. 2A-2B, 7A-7B and 8, multiplexer 1400/4400 receives a first input voltage of the external power supply mode (hereinafter referred to as a “first external input voltage”) VIN1_EXT from the power management integrated circuit 10, and selectively provides it as VIN1, to be subsequently included in VOUT_EXT, and provided in the analog power supply voltage AVDD to the power line to pixels PX in Fig. 14, in response to the activated multiplexer control signal MCTR), and wherein the pixels are configured to receive the external power supply voltage through the power supply line, and to emit light based on the external power supply voltage (regarding e.g. Figs. 2A and 14, the selectively provided voltage VIN1_EXT as VIN1, is subsequently included in VOUT_EXT, and provided in the analog power supply voltage AVDD to the power line to pixels PX in Fig. 14).
Kang discloses the controller is configured to deactivate the low-dropout enable signal, and is configured to activate the load enable signal, in a driving period after the power-on period (regarding Figs. 6-7, e.g. in a third period which “is a period after a third time point t3a′, and means the display period”, “the timing controller 11 applies the first control signal to the buck converter 160′ through the first line ELVDD_EN1”, and “does not apply the second control signal to the LDO regulator 161′ through the second line ELVDD_EN2”; para[0107]-para[0108]; para[0112]; para[0116]), wherein the low-dropout circuit is configured to reduce or block the internal power supply voltage to the power supply line in response to the deactivated low-dropout enable signal (since “In the third period, the timing controller 11 does not apply the second control signal to the LDO regulator 161′ through the second line ELVDD_EN2” it is clear that the LDO regulator 161′ blocks the voltage of the second level from being applied to the first power line ELVDD, accordingly; para[0107]-para[0108]; para[0113]-para[0114]; para[0116]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the controller is configured to deactivate the low-dropout enable signal, and is configured to activate the load switch enable signal, in a driving period after the power-on period, wherein the low-dropout circuit is configured to reduce or block the internal power supply voltage to the power supply line in response to the deactivated low-dropout enable signal, in the combination, for the advantage of applying a power voltage having lower noise only during a sensing period such that the pixel may be stably driven while reducing power consumption (para[0119]).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0415231), in view of Kang et al. (US 2022/0284855), and further in view of Wang (US 2008/0031025).
Regarding claim 8, Lee and Kang disclose all the claim limitations as applied above (see claim 1). In addition, Kang discloses a load switch circuit configured to reduce or block a power supply voltage to a power supply line in response to a deactivated load enable signal (regarding Figs. 6-7, e.g. “when the timing controller 11 applies a first control signal to the buck converter 160′ through the first line ELVDD_EN1, the buck converter 160′ may apply a voltage of a first level to the first power line ELVDD”; however, during a “first period… from a first time point t1a′ to a second time point t2a′”, “the timing controller 11 does not apply the first control signal to the buck converter 160′ through the first line ELVDD_EN1”, thus blocking a supply of the voltage of the first level to the first power line ELVDD in response to a deactivated first control signal through line ELVDD_EN1; para[0103]; para[0111]-para[0113]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the load switch circuit is configured to reduce or block the external power supply voltage to the power supply line in response to the deactivated load switch enable signal, in the combination, for the advantage of only applying a power voltage having lower noise such that the pixel may be stably driven during the sensing period (para[0119]).
However, Lee and Kang do not appear to expressly disclose the controller is configured to deactivate the load switch enable signal in response to an abnormal event of the display panel being detected.
Wang discloses a controller configured to deactivate a load switch enable signal in response to an abnormal event of a load circuit being detected (regarding Fig. 2, when load circuit 212 is e.g. an LED display device requiring stable operating current, “control signal generator 214 senses the current of the resistor 204 to generate the control signal Sc, so as to control the switch 202”, and “When the current of the resistor 204 increases to a predetermined maximum level, the control signal generator 214 turns off the switch 202 with the control signal Sc”, thus deactivating control signal Sc in response to an overcurrent of the LED display device; para[0005]; para[0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Lee’s and Kang’s combination, with the teachings in Wang’s invention, to have the controller is configured to deactivate the load switch enable signal in response to an abnormal event of the display panel being detected, for the advantage of maintaining current of a load circuit (display panel) within a specific range while reducing circuit complexity and production cost (para[0009]; para[0017]).
Regarding claim 9, Lee, Kang and Wang disclose all the claim limitations as applied above (see claim 8). In addition, Wang discloses the abnormal event comprises an overcurrent of the load circuit (regarding Fig. 2, when load circuit 212 is e.g. an LED display device requiring stable operating current, “When the current of the resistor 204 increases to a predetermined maximum level, the control signal generator 214 turns off the switch 202 with the control signal Sc”; para[0005]; para[0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the abnormal event comprises an overcurrent of the display panel, in the combination, for the advantage of maintaining current of the load circuit (display panel) within a specific range while reducing circuit complexity and production cost (para[0009]; para[0017]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0415231), in view of Kang et al. (US 2022/0284855), and further in view of Tokunaga (US 2014/0025978).
Regarding claim 10, Lee and Kang disclose all the claim limitations as applied above (see claim 1). However, Lee and Kang do not appear to expressly disclose the load switch circuit comprises: a first transistor connected between the power supply line and an external power supply circuit configured to generate the external power supply voltage; and a second transistor configured to selectively turn on the first transistor in response to the load switch enable signal.
Tokunaga discloses a switch circuit comprises: a first transistor connected between a power supply line and a power supply circuit configured to generate the power supply voltage (see circuit 201 in Fig. 1, comprising transistor 101 connected between power supply line connected to 202, and a power supply circuit that generates a power of the first power line V1); and a second transistor configured to selectively turn on the first transistor in response to a switch enable signal (see in Fig. 1, circuit 201 comprising transistor 102/103 configured to selectively turn on transistor 101 in response to S1/S2; para[0046]; para[0049]-para[0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Lee’s and Kang’s combination, with the teachings in Tokunaga’s invention, to have the load switch circuit comprises: a first transistor connected between the power supply line and an external power supply circuit configured to generate the external power supply voltage; and a second transistor configured to selectively turn on the first transistor in response to the load switch enable signal, for the advantage of controlling power supply or stop of power supply while reducing power consumption (para[0045]; para[0055]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0415231), in view of Kang et al. (US 2022/0284855) and Tokunaga (US 2014/0025978), and further in view of Lin et al. (US 9,942,957).
Regarding claim 11, Lee, Kang and Tokunaga disclose all the claim limitations as applied above (see claim 10). However, Lee, Kang and Tokunaga do not appear to expressly disclose the first transistor comprises a P-type metal oxide semiconductor (PMOS) transistor, and wherein the second transistor comprises an N-type bipolar junction transistor (BJT).
Lin discloses a switch circuit comprises a first transistor comprising a P-type metal oxide semiconductor (PMOS) transistor, and a second transistor comprising an N-type bipolar junction transistor (BJT) (see in Fig. 2, e.g. first control circuit 1041 comprises transistor 1031 which is a P-type MOSFET and transistor 1044 which is an NPN-type bipolar junction transistor (BJT); column 5, line 29; column 6, lines 57-59).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Lee’s, Kang’s and Tokunaga’s combination, with the teachings in Lin’s invention, to have the first transistor comprises a P-type metal oxide semiconductor (PMOS) transistor, and wherein the second transistor comprises an N-type bipolar junction transistor (BJT), for the advantage of the known better noise immunity offered by PMOS transistors, and the known fast switching offered by N-type BJTs.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0415231), in view of Kang et al. (US 2022/0284855) and Tokunaga (US 2014/0025978), and further in view of Jung et al. (US2015/0180244).
Regarding claim 14, Lee, Kang and Tokunaga disclose all the claim limitations as applied above (see claim 10). However, Lee, Kang and Tokunaga do not appear to expressly disclose the external power supply circuit comprises a switching mode power supply (SMPS) circuit in a host device.
Jung discloses an external power supply circuit comprises a switching mode power supply (SMPS) circuit in a host device (regarding Figs. 1B-2, “When an AC signal is input to the computer 120, a Switching Mode Power Supply (SMPS, not shown) that is part of the computer 120 converts the AC signal to DC signal”; “The DC signal may then be fed to the electronic device via a USB port and/or any other suitable type of interface”; para[0029]-para[0032]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Lee’s, Kang’s and Tokunaga’s combination, with the teachings in Jung’s invention, to have the external power supply circuit comprises a switching mode power supply (SMPS) circuit in a host device, for the advantage of converting an AC signal inputted to the host device to DC signal to then be fed to the electronic/display device, for quick power charging (para[0013]; para[0029]).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0415231), in view of Jung et al. (US2015/0180244), and further in view of Kang et al. (US 2022/0284855).
Regarding claim 19, Lee discloses an electronic device (see electronic device in Fig. 1; para[0025]) comprising:
an external power supply circuit configured to generate an external power supply voltage (regarding Figs. 1, 2A-2B, 7A-7B and 8, see power management integrated circuit 10 configured to generate “first external input voltage VIN1_EXT”; para[0042]; para[0078]; para[0083]-para[0084]; para[0100]); and
a display device configured to receive input image data and the external power supply voltage (see e.g. display device in Fig. 14; “The timing controller 8200 receives image data RGB… from the outside”; “power management integrated circuit 7000 may generate the first input voltage VIN1 and the second input voltage VIN2”, received by power module 8100; para[0007]; para[0025]; para[0099]-para[0102]), and comprising:
a display panel comprising pixels (see e.g. display panel 9000 comprising pixels PX as shown in Fig. 14);
a low-dropout circuit configured to generate an internal power supply voltage, and to provide the internal power supply voltage to the pixels through a power supply line (para[0040]-para[0042]; para[0044]; para[0054]; para[0072]; para[0083]; para[0100]; see in Figs. 2A-3B, 6A-6B and 8, analog low dropout (LDO) regulator 1120/4120 generates a first output voltage of the internal power supply mode (referred to as a “first internal output voltage”) VOUT1_INT having a specific level, which is included in analog power supply voltage AVDD provided through a power line to pixels PX in Fig. 14);
a load switch circuit configured to receive the external power supply voltage, and to selectively provide the external power supply voltage to the power supply line in response to a load switch enable signal (para[0042]; para[0078]; para[0083]-para[0084]; para[0100]; “multiplexer 4400 may receive the first internal input voltage VIN1_INT and the first external input voltage VIN1_EXT”; “The multiplexer 4400 may select one of the first internal input voltage VIN1_INT and the first external input voltage VIN1_EXT based on a multiplexer control signal MCTR”; see in Figs. 2A-2B, 7A-7B and 8, multiplexer 1400/4400 receives a first input voltage of the external power supply mode (hereinafter referred to as a “first external input voltage”) VIN1_EXT from the power management integrated circuit 10, and selectively provides it as VIN1, to be subsequently included in VOUT_EXT, and provided in the analog power supply voltage AVDD to the power line to pixels PX in Fig. 14); and
a controller configured to generate the load switch enable signal (para[0084]; “the multiplexer control signal MCTR may be controlled (or generated) by a separate controller (not illustrated) located inside or outside the power module 4000”; “For example, the controller (not illustrated) may generate the multiplexer control signal MCTR for determining whether a first power module 4100 operates in the internal power supply mode or the external power supply mode, so as to coincide with a power level that the system load 20 requires”).
However, Lee does not appear to expressly disclose a host device comprising the external power supply circuit; the display device configured to receive the external power supply voltage from the host device; the low-dropout circuit configured to generate an internal power supply voltage in response to a low-dropout enable signal; and the controller configured to generate the low-dropout enable signal.
Jung discloses a host device comprising the external power supply circuit, and a display device configured to receive external power supply voltage from the host device (regarding Figs. 1B-2, “When an AC signal is input to the computer 120, a Switching Mode Power Supply (SMPS, not shown) that is part of the computer 120 converts the AC signal to DC signal”; “The DC signal may then be fed to the electronic device via a USB port and/or any other suitable type of interface”; see e.g. device 100 including display device 207 receives DC power signal from the SMPS in the computer 120; para[0029]-para[0032]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Lee’s invention, with the teachings in Jung’s invention, to have a host device comprising the external power supply circuit; the display device configured to receive the input image data and the external power supply voltage from the host device, for the advantage of first converting an AC signal inputted to the host device to DC signal to then be fed to the electronic/display device, for quick power charging (para[0013]; para[0029]).
The combination of Lee and Jung does not appear to expressly disclose the low-dropout circuit configured to generate an internal power supply voltage in response to a low-dropout enable signal; and the controller configured to generate the low-dropout enable signal.
Kang discloses a low-dropout circuit configured to generate an internal power supply voltage in response to a low-dropout enable signal (para[0006]; para[0101]; para[0105]; regarding Figs. 1-2 and 6, “when the timing controller 11 applies a second control signal to the LDO regulator 161′ through the second line ELVDD_EN2, the LDO regulator 161′ may apply a voltage of a second level to the first power line ELVDD”); and a controller configured to generate the low-dropout enable signal (para[0105]; as shown in Fig. 6, timing controller 11 generates the second control signal applied through the second line ELVDD_EN2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Lee’s and Jung’s combination, with the teachings in Kang’s invention, to have the low-dropout circuit configured to generate the internal power supply voltage in response to a low-dropout enable signal; and the controller configured to generate the low-dropout enable signal and the load switch enable signal, for the advantage of a control configuration with which influence of noise may be minimized, and characteristic sensing accuracy of the pixel may be increased (para[0005]; para[0121]-para[0122]).
Regarding claim 20, Lee, Jung and Kang disclose all the claim limitations as applied above (see claim 19). In addition, Kang discloses the controller is configured to activate the low-dropout enable signal (regarding Figs. 6-7, during “The first period… from a first time point t1a′ to a second time point t2a′”, “the timing controller 11 applies a second control signal to the LDO regulator 161′ through the second line ELVDD_EN2, the LDO regulator 161′ may apply a voltage of a second level to the first power line ELVDD” and “the voltage of the second level may be a second power voltage used in the pixel PXij during the sensing period” in which characteristic of the pixel is sensed; para[0005]; para[0105]; para[0111]-para[0114]; para[0119]; para[0122]), and is configured to deactivate a load enable signal, in a power-on period or a sensing period of the display device (regarding Figs. 6-7, e.g. “when the timing controller 11 applies a first control signal to the buck converter 160′ through the first line ELVDD_EN1, the buck converter 160′ may apply a voltage of a first level to the first power line ELVDD”; however, during “The first period… from a first time point t1a′ to a second time point t2a′”, that is, the sensing period, “the timing controller 11 does not apply the first control signal to the buck converter 160′ through the first line ELVDD_EN1”, thus blocking a supply of the voltage of the first level to the first power line ELVDD in response to the deactivated first control signal through line ELVDD_EN1; para[0103]; para[0111]-para[0113]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the controller is configured to activate the low-dropout enable signal, and is configured to deactivate the load switch enable signal, in a power-on period or a sensing period of the display device, in the combination, for the advantage of only applying a power voltage having lower noise such that the pixel may be stably driven during a sensing period (para[0119]).
Allowable Subject Matter
Claims 12-13 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 12, Lee, Kang and Tokunaga disclose all the claim limitations as applied above (see claim 10).
Lin et al. (US 9,942,957) discloses a switch circuit comprising: a second resistor connected between a first terminal of a second transistor and a control electrode of the first transistor (see in Fig. 2, resistor R4 connected between a first terminal of transistor 1044 and a control electrode of transistor 1031; column 5, line 29; column 6, lines 57-59).
However, the prior art, taken alone or in combination, fails to teach or suggest the following limitations in combination with the rest of the claim, that is, the claim as a whole: “…the load switch circuit further comprises: a first resistor comprising a first terminal configured to receive the load switch enable signal, and a second terminal connected to a control electrode of the second transistor; a second resistor connected between a first terminal of the second transistor and a control electrode of the first transistor; a capacitor connected between a first terminal of the first transistor and the second resistor; and a third resistor connected in parallel with the capacitor”, as claimed in claim 12.
Regarding claim 13, would be allowable based on its dependence from claim 12.
Regarding claim 15, Lee and Kang disclose all the claim limitations as applied above (see claim 1). However, the prior art, taken alone or in combination, fails to teach or suggest the following limitations in combination with the rest of the claim, that is, the claim as a whole: “…the load switch circuit comprises: first transistors connected in parallel between the power supply line and an external power supply circuit configured to generate the external power supply voltage; and a second transistor configured to selectively turn on the first transistors in response to the load switch enable signal”, as claimed in claim 15.
Regarding claim 16, would be allowable based on its dependence from claim 15.
Claims 17-18 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 17, Lee et al. (US 2022/0415231) discloses a display device (see e.g. display device in Fig. 14; para[0007]; para[0025]; para[0099]) comprising:
a display panel comprising pixels (see e.g. display panel 9000 comprising pixels PX as shown in Fig. 14);
a low-dropout circuit configured to generate an internal power supply voltage, and to provide the internal power supply voltage to the pixels through a power supply line (para[0040]-para[0042]; para[0044]; para[0054]; para[0072]; para[0083]; para[0100]; see in Figs. 2A-3B, 6A-6B and 8, analog low dropout (LDO) regulator 1120/4120 generates a first output voltage of the internal power supply mode (referred to as a “first internal output voltage”) VOUT1_INT having a specific level, which is included in analog power supply voltage AVDD provided through a power line to pixels PX in Fig. 14);
a load switch circuit configured to receive an external power supply voltage, and to selectively provide the external power supply voltage to the power supply line in response to a load switch enable signal (para[0042]; para[0078]; para[0083]-para[0084]; para[0100]; “multiplexer 4400 may receive the first internal input voltage VIN1_INT and the first external input voltage VIN1_EXT”; “The multiplexer 4400 may select one of the first internal input voltage VIN1_INT and the first external input voltage VIN1_EXT based on a multiplexer control signal MCTR”; see in Figs. 2A-2B, 7A-7B and 8, multiplexer 1400/4400 receives a first input voltage of the external power supply mode (hereinafter referred to as a “first external input voltage”) VIN1_EXT from the power management integrated circuit 10, and selectively provides it as VIN1, to be subsequently included in VOUT_EXT, and provided in the analog power supply voltage AVDD to the power line to pixels PX in Fig. 14); and
a controller configured to generate the load switch enable signal (para[0084]; “the multiplexer control signal MCTR may be controlled (or generated) by a separate controller (not illustrated) located inside or outside the power module 4000”; “For example, the controller (not illustrated) may generate the multiplexer control signal MCTR for determining whether a first power module 4100 operates in the internal power supply mode or the external power supply mode, so as to coincide with a power level that the system load 20 requires”).
Kang et al. (US 2022/0284855) discloses a low-dropout circuit configured to generate an internal power supply voltage in response to a low-dropout enable signal (para[0006]; para[0101]; para[0105]; regarding Figs. 1-2 and 6, “when the timing controller 11 applies a second control signal to the LDO regulator 161′ through the second line ELVDD_EN2, the LDO regulator 161′ may apply a voltage of a second level to the first power line ELVDD”); and a controller configured to generate the low-dropout enable signal (para[0105]; as shown in Fig. 6, timing controller 11 generates the second control signal applied through the second line ELVDD_EN2).
Tokunaga (US 2014/0025978) discloses a load switch circuit comprises: a first transistor comprising a control electrode, a first terminal connected to an external power supply circuit configured to generate the external power supply voltage, and a second terminal connected to the power supply line (see circuit 201 in Fig. 1, comprising transistor 101 comprising a control electrode, a first terminal connected toa power supply circuit that generates a power of the first power line V1, and a second terminal connected to power supply line connected to 202); and a second transistor comprising a control electrode configured to receive the load switch enable signal, a first terminal, and a second terminal (see in Fig. 1, circuit 201 comprising transistor 102/103 comprising a control electrode configured to receive S1/S2, and first and second terminals).
Lin et al. (US 9,942,957) discloses a load switch circuit comprises a second resistor connected between the first terminal of the second transistor and the control electrode of the first transistor (see in Fig. 2, resistor R4 connected between a first terminal of transistor 1044 and a control electrode of transistor 1031; column 5, line 29; column 6, lines 57-59).
However, the prior art, taken alone or in combination, fails to teach or suggest the following limitations in combination with the rest of the claim, that is, the claim as a whole: “… the load switch circuit… comprising:… a first resistor; a second transistor comprising a control electrode configured to receive the load switch enable signal through the first resistor, a first terminal, and a second terminal configured to receive a ground voltage; a second resistor connected between the first terminal of the second transistor and the control electrode of the first transistor; a capacitor connected between the first terminal of the first transistor and the second resistor; and a third resistor connected in parallel with the capacitor…”, as claimed in claim 17.
Regarding claim 18, it is allowed based on its dependence from claim 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
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/GLORYVID FIGUEROA-GIBSON/Patent Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623