DETAILED ACTION
The present application, filed 02/04/2025, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-18 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 5-18, 20, and 21 of U.S. Patent No. 12,242,292. Although the claims at issue are not identical, they are not patentably distinct from each other because they recite a first voltage stepdown module including a first operational amplifier having a low voltage rail input, wherein an intermediate stepped down voltage is coupled to the low voltage rail input of the first voltage stepdown module.
Instant Application 19/044,697
Conflicting Patent US 12,242,292
1. A circuit comprising: a first voltage stepdown module including a first operational amplifier having a low voltage rail input, wherein an intermediate stepped down voltage is coupled to the low voltage rail input of the first voltage stepdown module.
1. A circuit comprising: a first voltage stepdown module having an intermediate stepped down voltage as an output, the intermediate stepped down voltage being coupled to a low voltage rail input of the first voltage stepdown module, wherein the first voltage stepdown module includes a first operational amplifier having the low voltage rail input; and a second voltage stepdown module including a second operational amplifier having the intermediate stepped down voltage as an input.
2. The circuit of claim 1, wherein the first voltage stepdown module comprises a low- dropout voltage regulator having a supply voltage and a reference voltage as inputs and the intermediate stepped down voltage as an output.
2. The circuit of claim 1, wherein the first voltage stepdown module comprises a low- dropout voltage regulator having a supply voltage and a reference voltage as inputs and the intermediate stepped down voltage as an output.
3. The circuit of claim 1, wherein the first voltage stepdown module comprises multiple low-dropout voltage regulators in series, a supply voltage is an input to a first low- dropout voltage regulator, an output voltage of a last low-dropout voltage regulator is the intermediate stepped down voltage, and each low-dropout voltage regulator has a reference voltage as an input.
3. The circuit of claim 1, wherein the first voltage stepdown module comprises multiple low-dropout voltage regulators in series, a supply voltage is an input to a first low-dropout voltage regulator, an output voltage of a last low-dropout voltage regulator is the intermediate stepped down voltage, and each low-dropout voltage regulator has a reference voltage as an input.
4. The circuit of claim 1, wherein: the first voltage stepdown module comprises: the first operational amplifier having a high voltage rail coupled to a supply voltage, a non-inverting input terminal coupled to a reference voltage, and an inverting input terminal coupled to a feedback signal; and a transistor having a first terminal coupled to the supply voltage, a gate terminal coupled to an output of the first operational amplifier, and a second terminal configured to output the intermediate stepped down voltage and coupled to a first terminal of a voltage divider; a second terminal of the voltage divider is coupled to ground; and a midpoint terminal of the voltage divider is configured to output the feedback signal.
4. The circuit of claim 1, wherein: the first voltage stepdown module comprises: the first operational amplifier having a high voltage rail coupled to a supply voltage, a non-inverting input terminal coupled to a reference voltage, and an inverting input terminal coupled to a feedback signal; and a transistor having a first terminal coupled to the supply voltage, a gate terminal coupled to an output of the first operational amplifier, and a second terminal configured to output the intermediate stepped down voltage and coupled to a first terminal of a voltage divider; a second terminal of the voltage divider is coupled to ground; and a midpoint terminal of the voltage divider is configured to output the feedback signal.
5. The circuit of claim 1, further comprising a second voltage stepdown module including a second operational amplifier having the intermediate stepped down voltage as an input, wherein the second voltage stepdown module further includes an output transistor having a first terminal coupled to the intermediate stepped down voltage.
21. The circuit of claim 1, wherein the second voltage stepdown module further includes an output transistor having a first terminal coupled to the intermediate stepped down voltage.
6. The circuit of claim 1, further comprising a second voltage stepdown module including a second operational amplifier having the intermediate stepped down voltage as an input, wherein a low-dropout voltage regulator of the second voltage stepdown module is an inverter-based low-dropout voltage regulator.
6. The circuit of claim 1, wherein a low-dropout voltage regulator of the second voltage stepdown module is an inverter-based low-dropout voltage regulator.
7. The circuit of claim 1, further comprising an internal reference voltage generator having a reference voltage as an input and an internally generated reference voltage as an output, the internally generated reference voltage being an input to a low-dropout voltage regulator of the first voltage stepdown module, the low-dropout voltage regulator having a supply voltage as an input and the intermediate stepped down voltage as a feedback input.
7. The circuit of claim 1, further comprising an internal reference voltage generator having a reference voltage as an input and an internally generated reference voltage as an output, the internally generated reference voltage being an input to a low-dropout voltage regulator of the first voltage stepdown module, the low-dropout voltage regulator having a supply voltage as an input and the intermediate stepped down voltage as a feedback input.
8. The circuit of claim 7, wherein the intermediate stepped down voltage is the low voltage rail input to the low-dropout voltage regulator.
8. The circuit of claim 7, wherein the intermediate stepped down voltage is the low voltage rail input to the low-dropout voltage regulator.
9. The circuit of claim 1, wherein a low-dropout voltage regulator of the first voltage stepdown module is implemented using an N-well on a substrate.
9. The circuit of claim 1, wherein a low-dropout voltage regulator of the first voltage stepdown module is implemented using an N-well on a substrate.
10. The circuit of claim 1, further comprising a second voltage stepdown module including a second operational amplifier having the intermediate stepped down voltage as an input, wherein a low-dropout voltage regulator of the first voltage stepdown module and a low-dropout voltage regulator of the second voltage stepdown module are inverter-based low-dropout voltage regulators.
10. The circuit of claim 1, wherein a low-dropout voltage regulator of the first voltage stepdown module and a low-dropout voltage regulator of the second voltage stepdown module are inverter-based low-dropout voltage regulators.
11. The circuit of claim 10, wherein the inverter-based low-dropout voltage regulator of the first voltage stepdown module is implemented using an N-well on a substrate.
11. The circuit of claim 10, wherein the inverter-based low-dropout voltage regulator of the first voltage stepdown module is implemented using an N-well on a substrate.
12. A method comprising: receiving an intermediate stepped down voltage at a low voltage rail input of a first operational amplifier of a first step down stage; and receiving the intermediate stepped down voltage at a second step down stage.
12. A method comprising: receiving an intermediate stepped down voltage at a low voltage rail input of a first step down stage, wherein the first voltage stepdown module includes a first operational amplifier having the low voltage rail input; and receiving the intermediate stepped down voltage at a second operational amplifier of a second step down stage.
13. The method of claim 12, wherein the intermediate stepped down voltage is within 0.2 volts of a target output voltage.
13. The method of claim 12, wherein the intermediate stepped down voltage is within 0.2 volts of a target output voltage.
14. The method of claim 12, further comprising: generating an internal reference voltage based on a reference voltage; and using the internal reference voltage to generate the intermediate stepped down voltage.
14. The method of claim 12, further comprising: generating an internal reference voltage based on a reference voltage; and using the internal reference voltage to generate the intermediate stepped down voltage.
15. The method of claim 12, further comprising stepping down an input voltage at least twice before stepping down to a target output voltage.
15. The method of claim 12, further comprising stepping down an input voltage at least twice before stepping down to a target output voltage.
16. A circuit comprising: an output transistor coupled to an intermediate stepped down voltage of a first stage transistor, wherein the first stage transistor and the output transistor are implemented in a shuffle layout style.
16. A circuit comprising: a first stage transistor configured to output an intermediate stepped down voltage; and an output transistor having a first terminal coupled to the intermediate stepped down voltage, wherein the first stage transistor and the output transistor are implemented in a shuffle layout style on a substrate.
17. The circuit of claim 16, further comprising an operational amplifier configured to receive the intermediate stepped down voltage as a low voltage rail input, wherein a reference voltage is coupled to a non-inverting input of the operational amplifier.
17. The circuit of claim 16, further comprising an operational amplifier configured to receive the intermediate stepped down voltage as a low voltage rail input, wherein a reference voltage is coupled to a non-inverting input of the operational amplifier.
18. The circuit of claim 16, further comprising a low-dropout voltage regulator including: an operational amplifier having a high voltage rail terminal coupled to the intermediate stepped down voltage and configured to receive a voltage reference signal as an input, the operational amplifier configured to output an output transistor control signal, wherein the output transistor further has a gate coupled to the output transistor control signal; and a voltage divider having a first terminal coupled to a second terminal of the output transistor, a second terminal coupled to ground, and a midpoint terminal configured to output a feedback voltage signal, which is input to the operational amplifier.
18. The circuit of claim 16, further comprising a low-dropout voltage regulator including: an operational amplifier having a high voltage rail terminal coupled to the intermediate stepped down voltage and configured to receive a voltage reference signal as an input, the operational amplifier configured to output an output transistor control signal; and a voltage divider having a first terminal coupled to a second terminal of the output transistor, a second terminal coupled to ground, and a midpoint terminal configured to output a feedback voltage signal, which is input to the operational amplifier.
20. The circuit of claim 16, further comprising a number of active components and a number of dummy devices implemented next to the number of active components, wherein the number of dummy devices each comprise a gate, a source, and a drain coupled together.
20. The circuit of claim 16, further comprising a number of active components and a number of dummy devices implemented next to the number of active components, wherein the number of dummy devices each comprise a gate, a source, and a drain coupled together.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over claim 12 of US 12,242,292 in view of Yang et al. (“Yang”, US 2018/0152187).
Re claim 19, Claim 12 of US 12,242,292 teaches the limitations as applied to the claim above but does not teach wherein the shuffle layout style provides alternating terminals of the first stage transistor and terminals of the output transistor along a particular line.
Yang teaches a device [Fig 5B] wherein a shuffle layout style provides alternating terminals of a first transistor [433] and terminals of a second transistor [434] along a particular line [paragraph 20]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified claim 12 of US 12,242,292 to include the features of Yang because it is used reduce mismatches that are induced by the density gradient effect, thus improving the utility of the device, which increases efficiency.
Conclusion
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAKAISHA JACKSON whose telephone number is (571)270-3111. The examiner can normally be reached on M-F 8:00-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LaKaisha Jackson/
Primary Examiner, Art Unit 2838
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