Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending in this action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/04/2025, 03/02/2026, 08/5/2025, 05/05/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,934,265. Although the claims at issue are not identical, they are not patentably distinct from each other because
Instant Application
US 11,934,265
As per claim 1:
tracking circuitry that implements multiple tracking circuit entries; and control circuitry configured to track, using multiple uncorrectable error (UE) tracking circuit entries,
detected uncorrectable errors associated with multiple respective memory locations,
wherein the UE tracking circuit entries include a source field that identifies a source of a given UE.
As per claim 6:
track, using multiple uncorrectable error (UE) tracking circuit entries,
detected uncorrectable errors associated with multiple respective locations ….
As per claim 7:
wherein the UE tracking circuit entries include a source field that identifies a source of a given UE.
As per claim 2:
wherein the source field is configured to encode sources that include at least the following sources: a memory error and a snoop response.
As per claim 8:
wherein the source field is configured to encode sources that include at least the following sources: a memory error, … a snoop response.
As per claim 3:
wherein the source field is further configured to encode a memory cache error.
As per claim 8:
wherein the source field is configured to encode ..a memory cache error.
As per claim 8:
wherein the multiple UE tracking circuit entries are not tagged.
As per claim 9:
wherein the multiple UE tracking circuit entries are not tagged
As per claim 9:
maintain corruption indicators for data blocks, including a … corruption indicator that indicates … data was determined to be corrupted …
As per claim 10:
maintain corruption indicators for data blocks, wherein a corruption indicator indicates that a data block was determined to be corrupted.
One of ordinary skill in the art would clearly recognize claims of current application is an obvious variation of the claimed subject matter of claims of patent US 11,934,265 because both recite “tracking circuitry that implements multiple tracking circuit entries … to track, using multiple uncorrectable error (UE) tracking circuit entries, detected uncorrectable errors associated with multiple respective memory locations, wherein the UE tracking circuit entries include a source field that identifies a source of a given UE” see above explanation.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 5, 8, 9, 11, 14, 16, 17 and 19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 and 14 recite the limitation "a memory cache error".
The recited limitation such as “"a memory cache error” renders this limitation indefinite because the previous limitations does not mention about a cache memory error so that a source field (data field) to encode (convert data) a memory cache error. It is unclear how a data field or a field of data or a data an encode an error at all.
Claim 5 and 16 recite the limitation "the corresponding data". There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "whether error information in a given entry is valid".
The recited limitation such as “error information in a given entry” renders this limitation indefinite because the previous limitations does not mention about an error information or a given entry. As such, it is unclear what error information in a given entry can be determined to valid or invalid.
Claims 11 and 19 recite the limitation "in response to a software signal indicating that software has read the entry”
The recited limitation “"in response to a software signal indicating that software has read the entry” renders this limitation indefinite because the previous limitation does not receive any software signal that software signal has the read entry”
Claims 9 and 17 recite limitation such as “maintain corruption indicators for data blocks, including a first corruption indicator …”
The recited limitation such as “maintain corruption indicators for data blocks, including a first corruption indicator” renders this limitation indefinite because the previous claim and limitation does not mention about determination a plurality of corruption indicator for data blocks”. The previous claim and limitation does not even mention about any data blocks or first data block at all. As such, it is unclear how it can maintain when the corruption indicators do not even exist for maintaining.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-8, 10-15, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (US 2022/0,350,715), and further in view of Kumar et al. (US 2020/0,117,526)
As per claim 1:
As per claim 12:
As per claim 20:
Zhou discloses
An apparatus, comprising: memory circuitry; one or more processors configured to execute program instructions, wherein at least some of the program instructions access data in the memory circuitry;
A method, comprising: executing, by one or more processors of a computing device, instructions, wherein at least some of the program instructions access data in a memory; and
A non-transitory computer-readable medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes: memory circuitry; one or more processors configured to execute program instructions, wherein at least some of the program instructions access data in the memory circuitry;
(Zhou, Figs 1-13)
(Zhou, Fig. 1, Memory Module 120, Memory 130, ECC 132, Controller 122, Error Information, Controller 140, Uncorrectable Error Analyzer 146…)
(Zhou, [0187] A machine readable storage medium can cause a machine to perform the functions or operations …that stores information in a form accessible by a machine (e.g., computing device))
tracking circuitry that implements multiple tracking circuit entries; and
(Zhou, Fig. 1, for Each Memory 130 of Memory Module 120 has ECC132 and ECS 134 to track multiple uncorrectable errors…)
(Zhou, UE uncorrectable error 250, DUE, Memory Fault Tracker 260
control circuitry configured to track, using multiple uncorrectable error (UE) tracking circuit entries, detected uncorrectable errors associated with multiple respective memory locations,
(Zhou, [0038] ECS 134 or a scrub engine of error control 152 can perform patrol scrubbing, which refers to performance of error checking … of all memory 130 within a set period, …Patrol scrubbing can generate CE and UE information … to indicate correctable errors and hard faults or uncorrectable errors detected in memory 130)
wherein the UE tracking circuit entries include a source that identifies a source of a given UE.
(Zhou, [0068] Controller 280 executes memory fault tracker (MFT) 260, which represents an engine to determine a component that caused an error…or a memory region associated with the faulty component…system to be monitored for memory errors)
(Zhou, [0070] UE 254 represents UE data for detected, uncorrectable errors (DUES) detected in data of memory 246)
(Zhou, [0071] …, defect detection 262 represents a UE analyzer that implements information from UAM 230 to identify a faulty component in memory 246 based on the historical error information correlated with system architecture information. With the identification of an error at the hardware component level, memory fault tracker 260 can specifically identify what memory region(s) are defective based on the faulty component)
(Zhou, [0044] … UE analyzer 146 … to determine a specific hardware component of memory that caused a detected UE or DUE... UE analyzer 146 operates after detection of a UE. UE analyzer 146 can use information from UAM 142 and correlation engine 144 to compute a confidence level for multiple hardware components of memory, based on historical error information correlated with the hardware configuration information. The confidence level can indicate a likelihood that a specific component caused a detected UE. … which component is most likely to have caused the UE. [0045] … UE analyzer 146 can compute confidence factors for multiple or all hardware component levels of the hardware architecture and determine that the component with a highest (or lowest, depending how the calculation is performed) score is the cause of the fault. In one example, UE analyzer 146 determines one component is the cause of the fault only if its confidence score exceeds all other confidence scores by a threshold. In the case of more than one confidence score within a threshold of each other, UE analyzer 146 can generate an indication that a determination cannot be made (e.g., an “unknown component failure”).)
(Zhou [0063] … UE analysis model (UAM) builder 220 to process data from dataset 210 to generate a model that indicates configurations with error patterns that are likely to result in a UE)
Zhou does not clearly disclose:
Field
Kumar discloses:
Field
(Kumar, [0068] uncorrected errors … be identified based on an inability of error correction circuitry to correct errors … using one or more type of error correction codes …DPAs having identified uncorrected errors may be … maintained with error location information 723-a (e.g., maintained in a lookup table (LUT)).
(Kumar, Data Structure field, Error Location Field, Over flag Field 46)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate error location field into the system in order to identify the location of address location of errors.
(Kumar, [0068] uncorrected errors … be identified based on an inability of error correction circuitry to correct errors … using one or more type of error correction codes …DPAs having identified uncorrected errors may be … maintained with error location information 723-a (e.g., maintained in a lookup table (LUT)).
(Kumar, Data Structure field, Error Location Field, Over flag Field 46)
As per claim 2:
As per claim 13:
Zhou-Kumar further discloses:
wherein the source field is configured to encode sources that include at least the following sources: a memory error and a snoop response.
(Zhou, [0068] Controller 280 executes memory fault tracker (MFT) 260, which represents an engine to determine a component that caused an error…or a memory region associated with the faulty component…system to be monitored for memory errors)
(Zhou, [0070] UE 254 represents UE data for detected, uncorrectable errors (DUES) detected in data of memory 246)
(Zhou, [0071] …, defect detection 262 represents a UE analyzer that implements information from UAM 230 to identify a faulty component in memory 246 based on the historical error information correlated with system architecture information. With the identification of an error at the hardware component level, memory fault tracker 260 can specifically identify what memory region(s) are defective based on the faulty component)
As per claim 3:
As per claim 14:
Zhou-Kumar further discloses:
wherein the source field is further configured to encode a memory cache error.
(Zhou, [0068] Controller 280 executes memory fault tracker (MFT) 260, which represents an engine to determine a component that caused an error…or a memory region associated with the faulty component…system to be monitored for memory errors)
(Zhou, [0070] UE 254 represents UE data for detected, uncorrectable errors (DUES) detected in data of memory 246)
(Zhou, [0071] …, defect detection 262 represents a UE analyzer that implements information from UAM 230 to identify a faulty component in memory 246 based on the historical error information correlated with system architecture information. With the identification of an error at the hardware component level, memory fault tracker 260 can specifically identify what memory region(s) are defective based on the faulty component)
(Zhou, region directory 264 detects whether any location of a cacheline associated with a memory access request falls into an identified defective memory region before writing a cacheline to memory 246)
As per claim 4:
As per claim 15:
Zhou-Kumar further discloses:
wherein the UE tracking circuit entries include a physical address field that indicates the memory location for an uncorrectable error.
(Zhou, [0068] Controller 280 executes memory fault tracker (MFT) 260, which represents an engine to determine a component that caused an error…or a memory region associated with the faulty component…system to be monitored for memory errors)
(Zhou, [0070] UE 254 represents UE data for detected, uncorrectable errors (DUES) detected in data of memory 246)
(Zhou, [0071] …, defect detection 262 represents a UE analyzer that implements information from UAM 230 to identify a faulty component in memory 246 based on the historical error information correlated with system architecture information. With the identification of an error at the hardware component level, memory fault tracker 260 can specifically identify what memory region(s) are defective based on the faulty component)
(Zhou, region directory 264 detects whether any location of a cacheline associated with a memory access request falls into an identified defective memory region before writing a cacheline to memory 246)
As per claim 7:
Zhou-Kumar further discloses:
wherein the UE tracking circuit entries include a valid field that indicates whether error information in a given entry is valid.
(Zhou, [0068] Controller 280 executes memory fault tracker (MFT) 260, which represents an engine to determine a component that caused an error…or a memory region associated with the faulty component…system to be monitored for memory errors)
(Zhou, [0070] UE 254 represents UE data for detected, uncorrectable errors (DUES) detected in data of memory 246)
(Zhou, [0071] …, defect detection 262 represents a UE analyzer that implements information from UAM 230 to identify a faulty component in memory 246 based on the historical error information correlated with system architecture information. With the identification of an error at the hardware component level, memory fault tracker 260 can specifically identify what memory region(s) are defective based on the faulty component)
(Zhou, region directory 264 detects whether any location of a cacheline associated with a memory access request falls into an identified defective memory region before writing a cacheline to memory 246)
As per claim 8:
Zhou-Kumar further discloses:
wherein the multiple UE tracking circuit entries are not tagged.
(Zhou, [0068] Controller 280 executes memory fault tracker (MFT) 260, which represents an engine to determine a component that caused an error…or a memory region associated with the faulty component…system to be monitored for memory errors)
(Zhou, [0070] UE 254 represents UE data for detected, uncorrectable errors (DUES) detected in data of memory 246)
(Zhou, [0071] …, defect detection 262 represents a UE analyzer that implements information from UAM 230 to identify a faulty component in memory 246 based on the historical error information correlated with system architecture information. With the identification of an error at the hardware component level, memory fault tracker 260 can specifically identify what memory region(s) are defective based on the faulty component)
(Zhou, region directory 264 detects whether any location of a cacheline associated with a memory access request falls into an identified defective memory region before writing a cacheline to memory 246)
As per claim 10:
As per claim 18:
Zhou does not disclose:
control circuitry configured to assert an overflow indicator in response to all of the UE tracking circuit entries being full.
Kumar discloses:
control circuitry configured to assert an overflow indicator in response to all of the UE tracking circuit entries being full.
(Kumar, [0068] uncorrected errors … be identified based on an inability of error correction circuitry to correct errors … using one or more type of error correction codes …DPAs having identified uncorrected errors may be … maintained with error location information 723-a (e.g., maintained in a lookup table (LUT)).
(Kumar, [0050] uncorrected errors exceeding the number of “m” fields, …the controller may utilize overflow flag field 430 to indicate that the capacity … structure was insufficient to indicate … uncorrected errors)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate the overflow of Kumar into the system in order to provide an indication that the uncorrected errors has exceed the maximum number of storage.
(Kumar, [0050] uncorrected errors exceeding the number of “m” fields, …the controller may utilize overflow flag field 430 to indicate that the capacity … structure was insufficient to indicate … uncorrected errors)
As per claim 11:
As per claim 19:
Zhou-Kumar further discloses:
control circuitry configured to invalidate an entry of the UE tracking circuit entries in response to a software signal indicating that software has read the entry.
(Zhou, [0071] …, defect detection 262 represents a UE analyzer that implements information from UAM 230 to identify a faulty component in memory 246 based on the historical error information correlated with system architecture information. With the identification of an error at the hardware component level, memory fault tracker 260 can specifically identify what memory region(s) are defective based on the faulty component)
(Zhou, region directory 264 detects whether any location of a cacheline associated with a memory access request falls into an identified defective memory region before writing a cacheline to memory 246)
Claim(s) 9, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (US 2022/0,350,715), and further in view of Kumar et al. (US 2020/0,117,526), in view of McNairy et al. (US 2014/0,281,747)
As per claim 9:
As per claim 17:
Zhou-Kumar further discloses:
control circuitry configured to: maintain corruption indicators for data blocks, including a first corruption indicator that indicates first data was determined to be corrupted based on an uncorrectable error; and
(Zhou, [0038] ECS 134 or a scrub engine of error control 152 can perform patrol scrubbing, which refers to performance of error checking … of all memory 130 within a set period, …Patrol scrubbing can generate CE and UE information … to indicate correctable errors and hard faults or uncorrectable errors detected in memory 130)
transmit, via a memory interface based on the first corruption indicator, a data and
(Zhou, [0068] Controller 280 executes memory fault tracker (MFT) 260, which represents an engine to determine a component that caused an error…or a memory region associated with the faulty component…system to be monitored for memory errors)
(Zhou, [0070] UE 254 represents UE data for detected, uncorrectable errors (DUES) detected in data of memory 246)
(Zhou, [0071] …, defect detection 262 represents a UE analyzer that implements information from UAM 230 to identify a faulty component in memory 246 based on the historical error information correlated with system architecture information. With the identification of an error at the hardware component level, memory fault tracker 260 can specifically identify what memory region(s) are defective based on the faulty component)
Zhou-Kumar does not mention parity
McNairy discloses:
Parity
(McNairy, [0031] … detect that the data 114 is uncorrectable based on the data qualifier 116. The data qualifier 116 may indicate the data source unit 102 as a generator of the uncorrectable data 114. The data qualifier 116 may indicate a type of error in the data 114 which may be, for example, an uncorrectable data error such as a multi-bit data error or parity error)
(McNairy, Fig. 1 shows a method of indicating parity error within data 114)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate McNairy’s method of qualifying the uncorrectable error into the system so that it would able to track whether the error is caused by data or parity of input data.
(McNairy, [0031] … detect that the data 114 is uncorrectable based on the data qualifier 116. The data qualifier 116 may indicate the data source unit 102 as a generator of the uncorrectable data 114. The data qualifier 116 may indicate a type of error in the data 114 which may be, for example, an uncorrectable data error such as a multi-bit data error or parity error)
(McNairy, Fig. 1 shows a method of indicating parity error within data 114)
Claims 5 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (US 2022/0,350,715), and further in view of Kumar et al. (US 2020/0,117,526), in view of Kim et al. (US 2020/0,026,441)
As per claim 5:
As per claim 16:
Zhou-Kumar further discloses:
wherein the UE tracking circuit entries include a
(Zhou, [0071] …, defect detection 262 represents a UE analyzer that implements information from UAM 230 to identify a faulty component in memory 246 based on the historical error information correlated with system architecture information. With the identification of an error at the hardware component level, memory fault tracker 260 can specifically identify what memory region(s) are defective based on the faulty component)
Zhou-Kumar does not disclose:
a client identifier field that indicates client circuitry
Kim discloses:
a client identifier field that indicates client circuitry
(Kim, Fig. 11, Host Interface 1040, ECC circuitry 1030)
(Kim, [0059] host information storage 222 may store the host information included in the system information read by the host access controller 220)
(Kim, Fig 3, shows host information storage 222 to store host information that access the memory device 100 as shown in figure 2)
(Kim, Fig. 9, Store …host information S911, Allow access of host to storage device S917)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Kim’s method of storing host information into the system in order to verify the host information before allowing to access the memory device.
As per claim 6:
Zhou-Kumar further discloses:
wherein the
(Zhou, [0071] …, defect detection 262 represents a UE analyzer that implements information from UAM 230 to identify a faulty component in memory 246 based on the historical error information correlated with system architecture information. With the identification of an error at the hardware component level, memory fault tracker 260 can specifically identify what memory region(s) are defective based on the faulty component)
Zhou-Kumar does not disclose:
a client identifier field that indicates client circuitry
Kim discloses:
a client identifier field that indicates client circuitry
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Kim’s method of storing host information into the system in order to verify the host information before allowing to access the memory device.
(Kim, Fig. 11, Host Interface 1040, ECC circuitry 1030)
(Kim, [0059] host information storage 222 may store the host information included in the system information read by the host access controller 220)
(Kim, Fig 3, shows host information storage 222 to store host information that access the memory device 100 as shown in figure 2)
(Kim, Fig. 9, Store …host information S911, Allow access of host to storage device S917)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Kim’s method of storing host information into the system in order to verify the host information before allowing to access the memory device.
As per claims 12-19:
Claims 12-19 recite similar limitations as claims 1-11. See rejection from above.
As per claim 20:
Claim 20 recites similar limitations as claim 1. See rejection from above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THIEN DANG NGUYEN whose telephone number is (571)272-9189. The examiner can normally be reached Monday-Friday 7 AM - 3:30 PM.
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/Thien Nguyen/ Primary Examiner, Art Unit 2111
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