Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Obviousness Type Double Patenting Rejection
1. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
2. Claims 1-20 of instant application 19045428 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-10 of Patent No. 12245464 in view of Kim (US 20130106839 A1). See the comparison bellow:
Claims of the Patent 12245464
Claims of the current application
19045428
Claim 1:
A display panel comprising:
a substrate including a main display area and a component area;
a main display element disposed on the main display area; a main pixel circuit overlapping with the main display element and electrically connected to the main display element;
an auxiliary display element disposed on the component area; and an auxiliary pixel circuit disposed outside of the component area and electrically connected to the auxiliary display element,
the auxiliary pixel circuit non-overlapping with the auxiliary display element in a plan view; wherein the auxiliary display element includes a plurality of light-emitting regions, and
Part of claim 1:
wherein a capacity of an auxiliary storage capacitor included in the auxiliary pixel circuit is greater than a capacity of a main storage capacitor included in the main pixel circuit.
2. The display panel of claim 1, wherein an area occupied by the auxiliary pixel circuit is greater than an area occupied by the main pixel circuit.
3. The display panel of claim 1, wherein the auxiliary storage capacitor comprises a first lower electrode, a second lower electrode, and an upper electrode, and wherein the first lower electrode and the second lower electrode are at a same layer as each other and spaced from each other.
4. The display panel of claim 1, wherein the component area includes a transmission area that at least partially surrounds the auxiliary display element.
5. The display panel of claim 4, wherein the transmission area is disposed between the auxiliary display element and the auxiliary pixel circuit.
6. The display panel of claim 1, further comprising a connecting line connecting the auxiliary display element to the auxiliary pixel circuit, and the connecting line comprises a transparent conductive oxide material.
7. The display panel of claim 6, wherein the connecting line comprises a first connecting line and a second connecting line, the first connecting line comprising a different material from that of the second connecting line, and wherein the first connecting line and the second connecting line are at a same layer as each other, and an end of the second connecting line covers an end of the first connecting line.
8. The display panel of claim 6, wherein the connecting line comprises a first connecting line and a second connecting line, the first connecting line comprising a different material from that of the second connecting line, and wherein the first connecting line and the second connecting line are at different layers from each other and connected to each other via a contact hole.
9. The display panel of claim 1, further comprising: an inorganic insulating layer between the substrate and the auxiliary display element; and a planarization layer between the inorganic insulating layer and the auxiliary display element, wherein the inorganic insulating layer has a hole or a groove at the component area, and the planarization layer is filled in the hole or the groove.
10. The display panel of claim 1, wherein at least one of the main display element or the auxiliary display element includes a pixel electrode, a first light-emitting region, a second light-emitting region, and an opposing electrode, and wherein the first light-emitting region and the second light-emitting region are spaced apart from each other on the pixel electrode.
Claim 1-10 corresponding to claims 11-20 in the current application 19045428
.
Claim 1.
A display panel comprising:
a substrate including a first area and a second area;
a plurality of first display elements disposed on the first area; a plurality of first circuits, one of the plurality of first circuits overlapping with a corresponding one of the plurality of first display elements, and being electrically connected to the corresponding one of the plurality of first display elements;
a plurality of second display elements disposed on the second area; and a plurality of second circuits disposed outside of the second area, one of the plurality of second circuits being electrically connected to a corresponding one of the plurality of second display elements,
the plurality of second circuits non-overlapping with the plurality of second display elements in a plan view, wherein the plurality of second circuits is arranged to at least partially surround the first area.
Claim 2.
wherein a capacity of a second storage capacitor included in one of the plurality of second circuits is greater than a capacity of a first storage capacitor included in one of the plurality of first circuits.
Claim 3. wherein the second storage capacitor comprises a first lower electrode, a second lower electrode, and an upper electrode, and wherein the first lower electrode and the second lower electrode are at a same layer as each other and spaced from each other.
Claim 4. wherein the second area includes a third area that at least partially surrounds at least one of the plurality of second display elements.
Claim 5. wherein the third area is disposed between at least some of the plurality of second display elements.
Claim 6. further comprising a connecting line connecting one of the plurality of second display elements to a corresponding one of the plurality of second circuits, wherein the connecting line comprises a transparent conductive oxide material.
Claim 7. wherein the connecting line comprises a first connecting line and a second connecting line, the first connecting line comprising a different material from that of the second connecting line, and wherein the first connecting line and the second connecting line are at a same layer as each other, and an end of the second connecting line contacts an end of the first connecting line.
Claim 8. wherein the connecting line comprises a first connecting line and a second connecting line, the first connecting line comprising a different material from that of the second connecting line, and wherein the first connecting line and the second connecting line are at different layers from each other and connected to each other via a contact hole.
Claim 9. The display panel of claim 1, further comprising: an inorganic insulating layer between the substrate and at least one of the plurality of second display elements; and a planarization layer between the inorganic insulating layer and at least one of the plurality of second display elements, wherein the inorganic insulating layer has a hole or a groove at the second area, and the planarization layer is filled in the hole or the groove.
Claim 10. wherein at least one of the plurality of second display elements includes a pixel electrode, a first light-emitting region, a second light-emitting region, and an opposing electrode, and wherein the first light-emitting region and the second light-emitting region are spaced apart from each other on the pixel electrode.
Claim 11-20 in Patent 12245464
Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims 1-20 in instant application obviously reads on the claims 1, 7, 8-10 and 17-18 of Patent No12245464 except the limitations “the one of the plurality of second circuits comprising a transistor for providing a driving current to the corresponding one of the plurality of second display elements”.
However, Kim (US 20130106839 A1) discloses pixel circuits (SP, Fig. 6) comprising a transistor (DST) for providing a drivinq current to the corresponding one of the plurality of second display elements ([0036-0040]) an the circuits (pixel circuit, see Fig. 6-8) overlapping with a corresponding one of the plurality of first display elements (pixel element with pixel electrode [see [0072-0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Patent 19045428 with the teaching of Kim, thereby improving the pixel luminance characteristics of the main display section.
2. Claims 1-20 of instant application 19045428 is rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claims 1-10 of Patent No. 11793032 over Kim (US 20130106839 A1) . See the comparison bellow:
Claims of the Patent 11793032
Claims of the current application
19045428
Claim 1.
A display panel comprising:
a substrate comprising a main display area, a component area, and a peripheral area;
a main sub-pixel at the main display area on the substrate; a main pixel circuit connected to the main sub-pixel,; an auxiliary sub-pixel comprising an auxiliary light emitting element at the component area on the substrate;
an auxiliary pixel circuit at the peripheral area on the substrate, and comprising an auxiliary storage capacitor, the auxiliary pixel circuit being spaced from the auxiliary light emitting element in a plan view by a transmission area between the auxiliary light emitting element and the auxiliary pixel circuit in a plan view;
and a connecting line extending between the auxiliary pixel circuit and the auxiliary light emitting element at the transmission area in a plan view to connect the auxiliary light emitting element of the auxiliary sub-pixel to the auxiliary pixel circuit,
Part of claim 1:
wherein a capacity of the auxiliary storage capacitor is greater than a capacity of the main storage capacitor.
7. The display panel of claim 1, wherein the auxiliary storage capacitor comprises a first lower electrode, a second lower electrode, and an upper electrode, and wherein the first lower electrode and the second lower electrode are at a same layer as each other and spaced from each other.
18. The display apparatus of claim 17, wherein each of the connecting lines at the component area comprises a transparent conductive oxide material.
8. The display panel of claim 1, wherein the connecting line comprises a first connecting line and a second connecting line, the first connecting line comprising a different material from that of the second connecting line, and wherein the first connecting line and the second connecting line are at a same layer as each other, and an end of the second connecting line covers an end of the first connecting line.
9. The display panel of claim 1, wherein the connecting line comprises a first connecting line and a second connecting line, the first connecting line comprising a different material from that of the second connecting line, and wherein the first connecting line and the second connecting line are at different layers from each other and connected to each other via a contact hole.
10. The display panel of claim 1, wherein the auxiliary sub-pixel comprises an auxiliary display element, wherein the display panel further comprises: an inorganic insulating layer between the substrate and the auxiliary display element; and a planarization layer between the inorganic insulating layer and the auxiliary display element, and wherein the inorganic insulating layer has a hole or a groove at the component area, and the planarization layer is filled in the hole or the groove.
Claim 17 corresponding to claims 1 and 10 in current application 19045428
Claims 1 and 11:
A display panel comprising:
a substrate including a first area and a second area;
a plurality of first display elements disposed on the first area; a plurality of first circuits, one of the plurality of first circuits overlapping with a corresponding one of the plurality of first display elements, and being electrically connected to the corresponding one of the plurality of first display elements;
a plurality of second display elements disposed on the second area; and a plurality of second circuits disposed outside of the second area, one of the plurality of second circuits being electrically connected to a corresponding one of the plurality of second display elements,
the plurality of second circuits non-overlapping with the plurality of second display elements in a plan view, wherein the plurality of second circuits is arranged to at least partially surround the first area.
Claims 2 and 12.
, wherein a capacity of a second storage capacitor included in one of the plurality of second circuits is greater than a capacity of a first storage capacitor included in one of the plurality of first circuits.
Claims 3 and 13. wherein the second storage capacitor comprises a first lower electrode, a second lower electrode, and an upper electrode, and wherein the first lower electrode and the second lower electrode are at a same layer as each other and spaced from each other.
Claims 6 and 16. further comprising a connecting line connecting one of the plurality of second display elements to a corresponding one of the plurality of second circuits, wherein the connecting line comprises a transparent conductive oxide material.
Claims 7 and 17. wherein the connecting line comprises a first connecting line and a second connecting line, the first connecting line comprising a different material from that of the second connecting line, and wherein the first connecting line and the second connecting line are at a same layer as each other, and an end of the second connecting line contacts an end of the first connecting line.
Claims 8 and 18: wherein the connecting line comprises a first connecting line and a second connecting line, the first connecting line comprising a different material from that of the second connecting line, and wherein the first connecting line and the second connecting line are at different layers from each other and connected to each other via a contact hole.
Claims 9 and 19. further comprising: an inorganic insulating layer between the substrate and at least one of the plurality of second display elements; and a planarization layer between the inorganic insulating layer and at least one of the plurality of second display elements, wherein the inorganic insulating layer has a hole or a groove at the second area, and the planarization layer is filled in the hole or the groove.
Claims 1 and 10 corresponding to claim 17 in the patent
Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims 1-3, 6-9, 11-13, 16-19 in instant application obviously reads on the claims 1-10 of Patent No 11793032 except the limitations “the one of the plurality of second circuits comprising a transistor for providing a driving current to the corresponding one of the plurality of second display elements”.
.
However, Kim (US 20130106839 A1) discloses pixel circuits (SP, Fig. 6) comprising a transistor (DST) for providing a drivinq current to the corresponding one of the plurality of second display elements ([0036-0040]) an the circuits (pixel circuit, see Fig. 6-8) overlapping with a corresponding one of the plurality of first display elements (pixel element with pixel electrode [see [0072-0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Patent 19045428 with the teaching of Kim, thereby improving the pixel luminance characteristics of the main display section.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1-5, 9-14, 18- 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zu (US 20190279547 A1) in view of Kim (US 20130106839 A1, IDS).
Regarding claim 1:
Zu (US 20190279547 A1) discloses a display panel (Fig. 2) comprising:
a substrate (110) including a first area (131) and a second area (132) (see Fig. 1-2);
a plurality of first display elements (pixel element) disposed on the first area (131);
a plurality of pixel (101), and being electrically connected to the corresponding one of the plurality of first display elements ([0024-0026]);
a plurality of second display elements (display element at 132) disposed on the second area (132) [0024-0026]; and
a plurality of second circuits (plurality of circuits at 120 ) disposed outside of the second area (132), one of the plurality of second circuits being electrically connected to a corresponding one of the plurality of second display elements (pixel at 132),
the plurality of second circuits non-overlapping with the plurality of second display elements in a plan view, wherein the plurality of second circuits (component circuit) is arranged to at least partially surround (surrounded at the top) the first area (see Fig. 1-2) (see [0032], [0032] In an embodiment, the display panel 100 further includes a flexible circuit board (not shown) electrically connected to the chip on film 120. Peripheral driving components such as resistors and capacitors are disposed on the flexible circuit board).
Note that Zu discloses the plurality of second circuits. However. Zu does not specifically discloses the second circuits comprising a transistor for providing a drivinq current to the corresponding one of the plurality of second display elements and disclose one of the plurality of first circuits overlapping with a corresponding one of the plurality of first display elements.
However, Kim (US 20130106839 A1) discloses pixel circuits (SP, Fig. 6) comprising a transistor (DST) for providing a drivinq current to the corresponding one of the plurality of second display elements ([0036-0040]) andthe circuits (pixel circuit, see Fig. 6-8) overlapping with a corresponding one of the plurality of first display elements (pixel element with pixel electrode [see [0072-0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zu with the teaching of Kim, thereby improving the pixel luminance characteristics of the main display section.
Regarding claims 2 and 12:
Note does not specifically disclose wherein a capacity of a second storage capacitor included in one of the plurality of second circuits is greater than a capacity of a first storage capacitor included in one of the plurality of first circuits.
Kim (US 20130106839) discloses a capacity of the second storage capacitor (CST2) included in one of the plurality of second circuits is greater than a capacity of a first storage capacitor included in one of the plurality of first circuits (i.e. main display capacitor CST1) ([0072]) (the main display section MP and the auxiliary display section SP. FIGS. 7 discloses Cst2 is the storage capacitor of the auxiliary display section SP and CST1 storage capacitor of main display section MP. The capacitance of the st2 should be more than 2 times larger than Cst1) .
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zu with the teaching of Kim , thereby improving the data voltage charging characteristics of the main display section.
Regarding claims 3 and 13:
Note that Zu in view of Kim does not specifically discloses wherein the second storage capacitor comprises a first lower electrode, a second lower electrode, and an upper electrode, and wherein the first lower electrode and the second lower electrode are at a same layer as each other and spaced from each other.
Kim discloses wherein the second storage capacitor (Cs2) comprises a first lower electrode (CGS2), a second lower electrode (CGs2), and an upper electrode (Ep1), and wherein the first lower electrode and the second lower electrode are at a same layer as each other and spaced from each other ( see Kim ‘6839, [0191]). Same motivation as applied to claim 1.
Regarding claims 4 and 14:
Zu discloses wherein the second area (132) includes a third area (area at 104) that at least partially surrounds at least one of the plurality of second display elements (see Fig. 2, [0024-0026]).
Regarding claim 5:
Zu discloses wherein the third area (120, component are) is disposed between at least some of the plurality of second display elements (see Fig. 2, [0024-0026]).
Regarding claims 9 and 18:
Zu in view of Kim discloses an inorganic insulating layer (PAS) between the substrate (110) and at least one of the plurality of second display elements (EP2); and a planarization layer (PAC) between the inorganic insulating layer (PAS) and at least one of the plurality of second display elements EP2 (see Kim, Fig. 8B, [0063]), wherein the inorganic insulating layerS) has a hole or a groove (CH2), and the planarization layer is filled in the hole or the groove (see Kim [0063]). Same motivation as applied to claim 1
Regarding claims 10 and 19:
Zu discloses wherein at least one of the plurality of second display elements (pixel at 132, see Fig. 2) includes a pixel electrode (101), a first light-emitting region (pixel element for 132), a second light-emitting region (pixel element at 132), and an opposing electrode (leading- out wire 104) , and wherein the first light-emitting region and the second light-emitting region are spaced apart from each other on the pixel electrode (see Fig. 2, [0028]).
Regarding claim 20:
Zu discloses wherein the component (component at 120) overlaps with the second area (132, see Fig. 2 [0024-0026]).
4. Claim(s) 6 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zu (US 20190279547 A1) in view of Kim (US 20130106839 A1, IDS) and further in view of Jung (US 20140191228, IDS).
Regarding claims 6 and 15:
Zu discloses a connecting linen(104) connecting one of the plurality of second display elements to a corresponding one of the plurality of second circuits, wherein the connecting line comprises a transparent material (see Fig. 2, 0028-0029).
Zu in view of Kim (‘0574) does not specifically discloses the connecting line comprises a transparent conductive oxide material.
Jung (US 20140191228) discloses wherein each of the connecting lines (DL) at the component area comprises a transparent conductive oxide material ([0052]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zu with the teaching of Kim and Jung, thereby forwarding accurate data voltage and improving the auxiliary pixel structure.
5. Claim(s) 7-8, 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zu (US 20190279547 A1) in view of Kim (US 20130106839 A1, IDS) and further in view of Jung and Park (US 20070159076, IDS).
Regarding claims 7 and 16:
Note that Zu in view of Kim disclose wherein the connecting line comprises a first connecting line (ADL) and a second connecting line (LL2) (see Fig. 8B), and wherein the first connecting line and the second connecting line are at a same layer as each other (i.e. substrate 106), and an end of the second connecting line (LL2) covers an end of the first connecting line (ADL) (see Kim, Fig. 8, [0097]).
Zu in view of Kim does not specifically disclose the first connecting line comprising a different material from that of the second connecting line.
Park (US 20070159076) discloses wherein the connecting line comprises the first connecting line (314) comprising a different material from that of the second connecting line (313) (see claim 4 park’s reference ([0094-00096], Fig. 6B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zu with the teaching of Kim , Jung and Park, thereby providing improved data transmission in the display device.
Regarding claims 8 and 17:
Zu in view of Kim does not specifically discloses wherein the connecting line comprises a first connecting line and a second connecting line, the first connecting line comprising a different material from that of the second connecting line, and wherein the first connecting line and the second connecting line are at different layers from each other and connected to each other via a contact hole.
Park (US 20070159076) discloses disclose wherein the connecting line comprises a first connecting line (314) and a second connecting line (313), the first connecting line comprising a different material from that of the second connecting line (see claim 4 park’s reference), and wherein the first connecting line and the second connecting line are at different layers (Fig. 6B) from each other and connected to each other via a contact hole (120) ([0094-00096]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zu with the teaching of Kim Jung and Park, thereby providing improved data transmission in the display device.
Responds to Applicant’s argument
6. Applicant’s argument filed on 12/29/2025 has been considered but are not persuasive. More specifically the Applicant argues Zu in view of Kim fails to disclose the limitations “the one of the plurality of second circuits comprising a transistor for providing a driving current to the corresponding one of the plurality of second display elements” as recited in claims 1 and 11”.
In responds Examiner disagrees with the Applicant’s point of view. Zu in view of Kim discloses pixel circuits (SP, Fig. 6) comprising a transistor (DST) for providing a driving current to the corresponding one of the plurality of second display elements ([0036-0040] and the circuits (pixel circuit, see Fig. 6-8) overlapping with a corresponding one of the plurality of first display elements (pixel element with pixel electrode [see [0072-0073]).
Conclusion
6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Inquiry
7. Any inquiry concerning this communication or earlier communication from the examiner should be directed to Shaheda Abdin whose telephone number is (571) 270-1673.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao could be reached at (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAHEDA A ABDIN/ Primary Examiner, Art Unit 2627