DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 02/04/2025. Claims 1-15 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2021/0312993 A1) in view of Park et al. (US 2024/0185939 A1) and further in view of Kayser et al. (US 2024/0377963 A1).
As per claim 1, Cho teaches a testing method for a memory device, comprising a memory array (e.g., item 100, fig. 2) including a memory array having a plurality of memory blocks (e.g. MB1 To MBk, [0034]-[0036]), peripheral circuitry including a row decoder (e.g., item 220, fig. 2) and column decoder (e.g., item 240, fig. 2), a voltage generation circuit (e.g., item 210) configured to generate operating voltages supplied to the memory array (e.g., [0038]), control logic (e.g., item 300) for controlling memory operations (e.g., [0036]), and a fail-bit counter (e.g., item 260) configured to determine the number of failed bits generated during memory testing (e.g. [0044]).
Thus, Cho teaches:
a memory array divided into a plurality of memory blocks (e.g., item 100, fig. 2);
selecting memory blocks through decoder circuitry (e.g. [0040]);
generating operating voltages for memory access operations (e.g. [0038]);
performing read and write test operations (e.g., [0042]);
receiving failed-bit counts after testing by means of a fail-bit counter (e.g., [0044]).
Cho does not teach:
adjusting a voltage value of at least one of the first reference voltage and the second reference voltage to sequentially perform an accessing operation on the memory blocks and receiving a plurality of failed bit counts of the memory blocks after the accessing operation; and counting a plurality of memory block numbers corresponding to a plurality of different voltage values of at least one of the first reference voltage and the second reference voltage and the failed bit counts.
However, Park discloses a memory testing method in which a test controller performs repeated test operations while varying a test operating parameter including a test reference current and corresponding bit-line voltage used during sensing operations, wherein the testing method comprising:
generating defect information from the test operation (e.g., [0065]);
counting fail bits resulting from the test operation (e.g., [0066]);
comparing the number of fail bits with a reference number (e.g., [0066]);
adjusting the bit-line voltage based on the comparison (e.g., [0067]);
repeating the testing operation until the failed-bit-count criterion is satisfied (e.g., [0067]).
Thus, Park teaches adjusting at least one reference voltage, repeatedly performing access operations under different voltage conditions, and obtaining failed-bit-count information corresponding to the different voltage settings.
Furthermore, Kayser discloses a method of analyzing memory reliability on a block-by-block basis, further comprising:
selecting memory blocks associated with weak word lines (e.g., [0023]);
determining failed-bit counts for the selected memory blocks (e.g., [0023]);
comparing the failed-bit counts with predetermined thresholds (e.g., [0023]);
identifying weak memory blocks based on the failed-bit-count information (e.g., [0023]);
using the identified block information to control subsequent programming operations (e.g., [0023]).
Kayser therefore teaches associating failed-bit-count information with identified memory blocks for memory-failure characterization.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the testing system of Cho by incorporating Park's known technique of repeatedly adjusting the reference voltage during memory testing while obtaining failed-bit-count information because Park expressly teaches that varying the operating voltage and evaluating the resulting failed-bit counts improves characterization of memory operation and enables determination of suitable operating voltages for reliable operation. It further would have been obvious to incorporate Kayser's known block-level failed-bit-count analysis into the modified testing system of Cho and Park so that the failed-bit-count results obtained at the different voltage settings are associated with the corresponding memory blocks, thereby identifying weak memory regions and improving memory reliability, programming decisions, and failure analysis. The combination merely applies known voltage-adjustment techniques together with known block-level failure analysis to a conventional memory testing architecture and yields the predictable result of improved memory characterization and optimization, consistent with KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Claim 2: Cho, Park and Kayser teach the testing method according to claim 1, further comprising: obtaining a first maximum test voltage value of the first reference voltage and a second maximum test voltage value of the second reference voltage. For instance, Park teaches adjusting the bit-line voltage based on comparison of fail bit count with reference number (e.g., [0067]) and repeating the testing operation until the failed-bit-count criterion is satisfied (e.g., [0067]). This inherently involves testing voltage values across a range to find suitable operating voltages. Park teaches that varying the operating voltage and evaluating the resulting fail bit counts enables determination of suitable operating voltages for reliable operation, which would include determining maximum test voltage values. Furthermore, Kayser teaches comparing failed-bit counts with predetermined thresholds and identifying weak memory blocks based on the failed-bit-count information (e.g., [0023]). This provides additional motivation for determining voltage limits to characterize block performance.
Claim 3: Cho, Park and Kayser teach the testing method according to claim 2, wherein the step of obtaining the first maximum test voltage value of the first reference voltage and the second maximum test voltage value of the second reference voltage comprises: setting the voltage value of the second reference voltage; incrementing the voltage value of the first reference voltage and receiving a first current value of the memory device; and when the first current value reaches a maximum current value, treating the voltage value of the first reference voltage as the first maximum test voltage value. For instance, Park teaches:
generating defect information from the test operation (e.g., [0065]);
counting fail bits resulting from the test operation (e.g., [0066]);
comparing the number of fail bits with a reference number (e.g., [0066]);
adjusting the bit-line voltage based on the comparison (e.g., [0067]);
repeating the testing operation until the failed-bit-count criterion is satisfied (e.g., [0067]).
Thus, Park teaches incrementing voltage (bit-line voltage) and evaluating a parameter (fail bit count) until a criterion is satisfied, which is directly analogous to incrementing the first reference voltage until a maximum current value is reached.
As per claim 4, Park teaches the same voltage-sweep technique described for Claim 3, which is symmetrical in application. Park teaches incrementally adjusting voltage until a criterion is satisfied (e.g., [0067]), which directly corresponds to incrementing the second reference voltage until a maximum current value is reached.
Claim 14: Cho, Park and Kayser teach the testing method according to claim 1, wherein the accessing operation comprises: performing a writing operation on a plurality of memory cells of a plurality of selected bit addresses connected to a selected bit line and different word lines (e.g., [0041] – Cho) and performing a reading operation on the memory cells of the plurality of selected bit addresses connected to the selected bit line and different word lines (e.g., [0041] – Cho).
Claim 15: Cho, Park and Kayser teach the testing method according to claim 1, wherein the accessing operation comprises: performing a writing operation on a plurality of memory cells of a plurality of selected bit addresses connected to a selected bit line and different word lines (e.g., [0041] – Cho) and adjusting at least one of the first reference voltage and the second reference voltage to perform a reading operation on the memory cells of the plurality of selected bit addresses connected to the selected bit line and different word lines (e.g., [0067] – Park).
Claim(s) 5-13 are rejected under 35 U.S.C. 103 as being unpatentable over Cho, Park and Kayser as applied to claim 4 above, and further in view of Hattori (JP H08-87838 A).
Claim 5: Cho, Park and Kayser teach the testing method according to claim 4, but fail to further teach comprising: based on a same failed bit count and a repair value, decrementing the voltage value of the first reference voltage from the first maximum test voltage value to sequentially obtain a first memory block number and a second memory block number in the memory block numbers; and when the second memory block number is greater than or equal to the first memory block number, modifying an operating memory block number to the second memory block number and treating the voltage value of the first reference voltage corresponding to the second memory block number as a first operation voltage value, wherein the repair value is any real number.
However, Park teaches adjusting voltage based on fail bit count comparison (e.g., [0067]) and repeating test operations until a criterion is satisfied. This provides the basis for iteratively adjusting voltage while monitoring a parameter (failed bit count) to find an optimal value. Furthermore, Kayser teaches:
determining failed-bit counts for the selected memory blocks (e.g., [0023]);
comparing the failed-bit counts with predetermined thresholds (e.g., [0023]);
identifying weak memory blocks based on the failed-bit-count information (e.g., [0023]);
using the identified block information to control subsequent programming operations (e.g., [0023]).
This directly supports associating failed-bit-count results with memory block numbers and using that information to control memory operations. And Hattori teaches:
measuring bit errors for each logical storage block (e.g., [0009]);
storing the number of errors for each block (e.g., [0009]);
using an error storage address that corresponds to the block number (e.g., [0009]);
This explicitly teaches counting memory block numbers corresponding to failed-bit-count results. Therefore, it would have been obvious to one of ordinary skill in the art to combine the teachings of Park (iterative voltage adjustment based on fail bit count), Kayser (block-level FBC analysis and using block information for programming decisions), and Hattori (storing error count with block numbers). Applying these teachings to Cho's testing system yields the claimed method of decrementing voltage from a maximum value, obtaining memory block numbers at different voltage levels based on failed bit count, comparing block numbers, and modifying an operating block number to determine an operation voltage value.
As per claim 12, the claimed features are rejected similarly to claim 5.
Claim 6: Cho, Park, Kayser and Hattoti teach the testing method according to claim 5, wherein the first operation voltage value is a reading operation voltage value generated by a reading operation in the accessing operation, wherein the testing method further comprises: when the second current value reaches a target current value, treating the voltage value of the second reference voltage as a target voltage value; and when the voltage value of the second reference voltage is equal to the target voltage value, determining the reading operation voltage value to be an optimal reading voltage value. For instance, Park teaches adjusting bit-line voltage based on comparison of fail bit count with a reference number (e.g., [0066-0067], and repeating the test operation until a criterion is satisfied. Park further teaches that varying the operating voltage and evaluating the resulting parameter enables determination of suitable operating voltages for reliable operation. Therefore, it would have been obvious to one of ordinary skill in the art to apply Park's teaching of determining suitable operating voltages to the reading operation in Cho's testing system. Park expressly teaches that varying the operating voltage and evaluating the resulting parameter enables determination of suitable operating voltages. When a target current value is reached, treating the voltage as a target value and determining it as an optimal reading voltage is a straightforward application of Park's teachings.
Claim 7: Cho, Park, Kayser and Hattoti teach the testing method according to claim 6, wherein the first operation voltage value is a writing operation voltage value generated by a writing operation in the accessing operation, wherein the testing method further comprises: when the second current value reaches a target current value, treating the voltage value of the second reference voltage as a target voltage value; and when the voltage value of the second reference voltage is equal to the target voltage value, determining the writing operation voltage value to be an optimal writing voltage value. For instance, Park teaches the same voltage-determination technique described for Claim 6, which applies symmetrically to writing operations. Therefore, it would have been obvious to one of ordinary skill in the art to apply Park's teaching of determining suitable operating voltages to the writing operation in Cho's testing system. The same rationale that applies to Claim 6 applies equally to Claim 7.
Claim 8: Cho, Park, Kayser and Hattoti teach the testing method according to claim 7, but fail to teach that the reading operation voltage value is less than the target voltage value, and the writing operation voltage value is greater than the target voltage value. However, this limitation is a straightforward consequence of the voltage relationships inherent in the methods of Claims 6 and 7. A person of ordinary skill would recognize that, in typical memory operation, the reading voltage is lower than the target (verify/program) voltage, and the writing (program) voltage is higher than the target voltage. This is a well-known relationship in memory testing that would be inherent in the claimed methods.
Claim 9: Cho, Park, Kayser and Hattoti teach the testing method according to claim 7, further comprising: determining operation parameters of the memory blocks according to the writing operation voltage value and the reading operation voltage value. For instance, Park teaches determining suitable operating voltages for reliable operation (e.g., [0067]), which inherently includes determining operation parameters based on those voltages. And Kayser teaches using identified block information (including FBC and weak block identification) to control subsequent programming operations (e.g., [0023]), which is consistent with determining operation parameters based on characterized block performance. Therefore, it would have been obvious to one of ordinary skill in the art that once optimal reading and writing voltage values are determined (as taught in Claims 6-7 and supported by Park), operation parameters for the memory blocks would naturally be derived from those values. This is a straightforward application of the determined voltages.
Claim 10: Cho, Park, Kayser and Hattoti teach the testing method according to claim 7, further comprising: when the reading operation voltage value is first determined, maintaining the reading operation voltage value and adjusting the first reference voltage in the writing operation to obtain the writing operation voltage value; and when the writing operation voltage value is first determined, maintaining the writing operation voltage value and adjusting the first reference voltage in the reading operation to obtain the reading operation voltage value. For instance, Park teaches an iterative testing process where parameters are adjusted until a criterion is satisfied (e.g., [0067]). This inherently includes maintaining some parameters while adjusting others—a standard technique in optimization processes. Therefore, it would have been obvious to one of ordinary skill in the art that once one operation voltage value (e.g., reading) is determined, the other (e.g., writing) can be obtained by maintaining that voltage and adjusting the first reference voltage. This is a standard sequential optimization technique that would be applied based on Park's iterative adjustment teaching.
Claim 11: Cho, Park, Kayser and Hattoti teach the testing method according to claim 5, further comprising: when the second memory block number is less than the operating memory block number, continuing to decrementing the voltage value of the first reference voltage to sequentially obtain a third memory block number in the memory block numbers; and when the third memory block number is greater than or equal to the operating memory block number, modifying the operating memory block number to the third memory block number and treating the voltage value of the first reference voltage corresponding to the third memory block number as a first operation voltage value. For instance, Park teaches an iterative process of adjusting voltage until a criterion is satisfied (e.g., [0067]), which provides the basis for the iterative decrementing claimed. Besides, Kayser teaches determining failed-bit counts for selected memory blocks, identifying weak memory blocks based on FBC information, and using identified block information to control subsequent programming operations (e.g., [0023]). This supports the block number comparison and modification logic. Finally, Hattori teaches storing error count per logical storage block with block numbers (e.g., [0009]), supporting the block number tracking claimed. Therefore, it would have been obvious to one of ordinary skill in the art to apply Park's iterative voltage adjustment technique (decrementing voltage until a criterion is satisfied) to the block-level framework of Kayser and Hattori, where block numbers are tracked and compared. The claimed logic of continuing to decrement until a third block number satisfies a comparison with the operating block number is a straightforward extension of these teachings.
As per claim 13, the claimed features are rejected similarly to claim 11 above.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 7/22/2026
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