DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 18 and 19 are objected to because of the following informalities:
Claim 18, line 4, should read as, “providing, based on the receiving a command to exit the self refresh mode, an indication . . .”
Claim 19, line 3, should read as, “wherein the providing the indication of a refresh operation in relation to the memory bank of the multiple memory banks comprises . . .”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-11, 13, and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sancon et al. (US 20230343380 A1; hereinafter "Sancon").
Regarding claim 1, Sancon discloses:
An apparatus (FIG. 2: computing system 200) comprising:
a memory device (FIG. 2: memory device 108) comprising:
at least one memory array comprising multiple memory banks (FIG. 2: memory array 216; FIG. 5: memory die 502 and memory banks 520); and
refresh logic coupled to the at least one memory array (FIG. 2: refresh control logic 206; FIG. 5: Refresh control logic 506), the refresh logic configured to:
refresh the multiple memory banks in a self-refresh mode (para. [0018]: “a memory device may perform a self-refresh operation on all banks of the multiple banks within the memory device”);
receive a command to exit the self-refresh mode (para. [0023]: “Signaling indicative of a command to exit the self-refresh mode may be asserted before at least one current word line is refreshed in each bank of the multiple banks of the memory device.”; para. [0080]: “the refresh control logic 506 exits the self-refresh mode in response to receiving, from the memory controller 522, signaling indicative of a command to exit the self-refresh mode.”); and
provide, based on the command to exit the self-refresh mode, an indication of a refresh operation in relation to a memory bank of the multiple memory banks (para. [0023]: “For example, the logic of the memory device may store in a register an indication of which banks or sets of banks have been refreshed (e.g., for a given refresh counter) while the memory device is in a self-refresh mode.”; para. [0041]: “The refresh controller 116 may make the determination of whether the self-refresh operation is currently being performed in response to receiving the command to exit the self-refresh mode.”).
Regarding claim 2: Sancon discloses:
the indication of the refresh operation in relation to the memory bank of the multiple memory banks comprises an indication that the refresh operation is in progress on the memory bank when the command to exit the self-refresh mode is being processed (FIG. 5 and para. [0076]: “. . . the value stored within the bank status register 510 that corresponds to the given bank may be altered (e.g., written) to a value that indicates that a self-refresh operation has been performed on the bank. In this way, the bank status register 510 may be used to track progress on the self-refresh operations of the banks 518.”).
Regarding claim 3, Sancon discloses:
the indication of the refresh operation in relation to the memory bank of the multiple memory banks comprises a Boolean indication that one or more memory banks of the multiple memory banks has a refresh operation in progress or that no memory bank of the multiple memory banks has a refresh operation in progress (FIG. 5 and para. [0076]: “. . . the bank status register 510 may be used to track progress on the self-refresh operations of the banks 518.”—the term “Boolean indication” is interpreted to refer to the fundamental data type of digital computing; thereby, an inherent characteristic of the bank status register 510).
Regarding claim 5, Sancon discloses:
the indication of the refresh operation in relation to the memory bank of the multiple memory banks comprises an identification of a subset of the multiple memory banks, the subset having the refresh operation in progress (para. [0025]: “the memory device may only initiate self-refresh operations in a proper subset of the multiple banks (i.e., where a proper subset of banks is fewer than all banks of the multiple banks) of the memory device.”; FIG. 5 and para. [0076]: “. . . the bank status register 510 may be used to track progress on the self-refresh operations of the banks 518.”).
Regarding claim 6, Sancon discloses:
the identification of the subset of the multiple memory banks that has the refresh operation in progress comprises at least one individual memory bank of the multiple memory banks (FIG. 5 and para. [0076]: “. . . the bank status register 510 may be used to track progress on the self-refresh operations of the banks 518.”).
Regarding claim 7, Sancon discloses:
the identification of the subset of the multiple memory banks that has the refresh operation in progress comprises at least one individual bank group of the multiple memory banks (para. [0026]: “The bank-level self-refresh operations may be tracked using registers. For example, responsive to a self-refresh operation being performed on a set of banks, a value may be set within an associated register to indicate that the refresh operation has been performed on that set of banks.”).
Regarding claim 8, Sancon discloses:
the memory device further comprises one or more registers comprising multiple bits configured to represent the identification of the subset of the multiple memory banks (para. [0026]: “The bank-level self-refresh operations may be tracked using registers. For example, responsive to a self-refresh operation being performed on a set of banks, a value may be set within an associated register to indicate that the refresh operation has been performed on that set of banks.”; para. [0094]: “The refresh controller 116 (e.g., of FIG. 5) can write a value to at least one bit of the bank status register 510 corresponding to the first set of banks 704 to indicate that the refresh operations have been completed on the first set of banks 704.”).
Regarding claim 9, Sancon discloses:
each respective bit of the multiple bits corresponds to a respective identification of a respective part of the subset of the multiple memory banks (para. [0095]: “. . . the refresh controller 116 can write a value to at least one bit of the bank status register 510 corresponding to the second set of banks 706 to indicate that the refresh operations have been completed on the second set of banks 706”); and
the refresh logic is configured to store a value in a bit of the multiple bits based on whether a refresh operation is in progress for the respective part of the subset of the multiple memory banks with regard to receipt of the command to exit the self-refresh mode (para. [0095]: “. . . the self-refresh mode 702 is exited before the second set of self-refresh operations are performed on the second set of one or more word lines within the third set of banks 708. In some instances, the self-refresh mode 702 is exited in response to receipt of signaling that is transmitted from the memory controller and that indicates a command to exit the self-refresh mode 702.”).
Regarding claim 10, Sancon discloses:
the refresh logic is configured to provide the indication of the refresh operation in relation to the memory bank of the multiple memory banks by transmitting the indication of the refresh operation based on the command to exit the self-refresh mode (FIG. 11: steps 1102 and 1104; para. [0115]: “Optionally at 1104, signaling indicative of a first set of banks that have performed a refresh operation of the first type within the self-refresh mode 702 may be received [by the memory controller 522].”—receiving requires transmission).
Regarding claim 11, Sancon discloses:
the refresh logic is configured to transmit the indication of the refresh operation based on the command to exit the self-refresh mode and before receiving an external command (FIG. 11: steps 1102 and 1104; para. [0115]: “at 1104, signaling indicative of a first set of banks that have performed a refresh operation of the first type within the self-refresh mode 702 may be received.” (emphasis added); para. [0075]: “During a self-refresh operation, the memory device may be unable to perform some functions, such as responding to certain activation commands and data read/write requests.”—the indication of the refresh operation may be transmitted before receiving an external command since the memory device does not respond to activation commands and read/write requests during a self-refresh operation).
Regarding claim 13, Sancon discloses:
the refresh logic is configured to provide the indication of the refresh operation in relation to the memory bank of the multiple memory banks based on the command to exit the self-refresh mode and responsive to an external command (FIG. 11: steps 1102 and 1104; para. [0041]: “The memory controller 114 can transmit commands to the memory device 108 (e.g., through the refresh controller 116), including a command that causes the memory device 108 to enter or exit a self-refresh mode.”)
Regarding claim 18, Sancon discloses:
A method for a memory device (FIG. 2: memory device 108), the method comprising:
refreshing, in a self-refresh mode, multiple memory banks of at least one memory array (para. [0018]: “a memory device may perform a self-refresh operation on all banks of the multiple banks within the memory device”);
receiving a command to exit the self-refresh mode (para. [0023]: “Signaling indicative of a command to exit the self-refresh mode may be asserted before at least one current word line is refreshed in each bank of the multiple banks of the memory device.”; para. [0080]: “the refresh control logic 506 exits the self-refresh mode in response to receiving, from the memory controller 522, signaling indicative of a command to exit the self-refresh mode.”; FIG. 10: step 1004; FIG. 11: step 1102); and
providing, based on the receiving, an indication of a refresh operation in relation to a memory bank of the multiple memory banks (para. [0023]: “For example, the logic of the memory device may store in a register an indication of which banks or sets of banks have been refreshed (e.g., for a given refresh counter) while the memory device is in a self-refresh mode.”; para. [0041]: “The refresh controller 116 may make the determination of whether the self-refresh operation is currently being performed in response to receiving the command to exit the self-refresh mode.”; FIG. 11: step 1104).
Regarding claim 19, Sancon discloses:
receiving a command to transmit the indication of the refresh operation, wherein the providing comprises transmitting the indication of the refresh operation in response to the receiving of the command to transmit the indication of the refresh operation (para. [0115]: “Optionally at 1104, signaling indicative of a first set of banks that have performed a refresh operation of the first type within the self-refresh mode 702 may be received [by the memory controller 522] . . . The signaling may be transmitted responsive to the memory controller 522 transmitting signaling indicative of a request to read counter values from one or more registers 208.”).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 18 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of U.S. Patent No. 12,462,862. Although the claims at issue are not identical, they are not patentably distinct from each other because Claim 17 of U.S. Patent No. 12,462,862 discloses a method teaching or suggesting:
refreshing, in a self-refresh mode, multiple memory banks of at least one memory array (“at least one bank that has performed a refresh operation”);
receiving a command to exit the self-refresh mode (“transmitting, from logic to a memory die, signaling indicative of a command to exit a self-refresh mode”); and
providing, based on the receiving, an indication of a refresh operation in relation to a memory bank of the multiple memory banks (“receiving, from the memory die at the logic, signaling indicative of: a first set of at least one bank that has performed a refresh operation of a first type on a first set of at least one word line within the self-refresh mode”).
Allowable Subject Matter
Claim 20 is allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding independent claim 20, the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed limitation(s) of “a memory controller comprising: . . . an interface . . . and refresh logic coupled to the interface, the refresh logic configured to: transmit, from the interface, a command to exit a self-refresh mode; and receive, via the interface, an indication of a refresh operation pertaining to exiting the self-refresh mode and in relation to a memory bank of the multiple memory banks,” in combination with the other limitations recited in the claim. That is, the limitations of claim 20 are interpreted to map to the memory controller 114 and refresh logic 118 of FIG. 1; and refresh logic 118 and interface 506 which are all external to the memory device 108.
Claims 4, 12, and 14-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
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/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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