DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/05/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims uses the term “blind erase option” and “blind erase operation.” However, the specification did not give a clear definition for the terms. The specification gave scenarios for these terms, but did not give a clear definition. In addition, if the blind erase operation is an erase operation without a pre-verify operation, then claims 4-7 and 12-14 are indefinite because the claims require a pre-verification operation. Therefore, the claims are indefinite.
Claims 7 and 14 recite “during the fast erase operation, the control circuit is configured to perform a normal erase operation…” It is confusing when the erase operation is considered fast erase operation, but in one scenario, the erase operation perform normal erase operation. Therefore, the erase operation is normal erase operation and not a fast erase operation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong et al. (US 2017/0125107 A1).
Regarding claim 1, Hong et al. teaches a memory device comprising:
a plurality of blocks, each block including memory cells; and a control circuit configured to enable a blind erase option and perform a blind erase operation on a target block among the plurality of blocks, wherein the control circuit, during the blind erase operation, is configured to perform an erase pulse applying operation on the target block without performing an erase verifying operation on the target block (Fig. 9, the memory device enable the multi-erase operation for the memory blocks. In erase operation 510, the memory device perform the erase operation without performing an erase verifying operation, ¶0081).
Regarding claim 2, Hong further teaches the memory device according to claim 1, wherein, during the blind erase operation, one erase pulse is applied to the target block (erase pulse is applied during step 513).
Regarding claim 3, Hong further teaches the memory device according to claim 1, wherein the control circuit is configured to enable the blind erase option in response to a setting command set for enabling the blind erase option, and perform the blind erase operation in response to an erase command set for the target block, and wherein the erase command set is continuous to the setting command set (Fig. 9, the multi-erase section 510 is performed in response to an erase command).
Regarding claim 4, Hong further teaches the memory device according to claim 1, wherein the control circuit is configured to enable a pre-erase verifying option, and perform a fast erase operation on the target block (a fast erase operation is given the broadest reasonable interpretation to mean an erase operation, because the claims and specification did not provide a measurement for what can be considered a fast erase operation. Therefore, any erase operation can be considered a fast erase operation. Hong teaches in Fig. 9, a pre-erase verifying option in step 522 and the fast erase operation is step 525).
Regarding claim 5, Hong further teaches the memory device according to claim 4, wherein the control circuit is configured to enable the pre-erase verifying option in response to a setting command set for enabling the pre-erase verifying option, and perform the fast erase operation in response to an erase command set for the target block, and wherein the erase command set is continuous to the setting command set (The memory controller will provide commands to the memory device to perform the operation of the memory device, such as providing a command to perform step 522 and 525).
Regarding claim 6, Hong further teaches the memory device according to claim 5, wherein, during the fast erase operation, the control circuit is configured not to perform an erase pulse applying operation on the target block before performing a pre-erase verifying operation on the target block (Fig. 9, the Erase Selected Memory Block 525 is not performed before the pre-erase verifying operation 522).
Regarding claim 7, Hong further teaches the memory device according to claim 6, wherein, during the fast erase operation, the control circuit is configured to perform a normal erase operation on the target block in response to a determination that the pre-erase verifying operation fails (Fig. 9, when the pre-erase verifying operation fails in step 522. The memory device will perform an erase operation on selected memory block in step 525).
Regarding claims 8-20, the claims have similar limitations as claims 1-7. Therefore, the claims are rejected under the same grounds of rejection for the same reasoning.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824
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