DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7-8, and 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 20220383965 A1; hereinafter "Yang").
Regarding claim 1, Yang discloses:
A method of operating a memory device (memory device 100), comprising the steps of:
preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines (FIGs. 6A-6F), a selected word line of a plurality of word lines being programmed according to a storage scheme that includes at least three data states (FIG. 7B: data states S1-S7);
during a sensing operation, for a set duration, discharging a sensing capacitor through a selected NAND string that includes a selected memory cell to be read (FIG. 26: step 2605);
after discharging the sensing capacitor for the set duration, conducting a first comparison of a voltage at a sense node to a trip voltage (FIG. 26: step 2607); and
applying a first voltage to an opposite side of the sensing capacitor from the sense node, and then conducting a second comparison of the voltage at the sense node to the trip voltage (FIG. 26: step 2611).
Regarding claim 7, Yang discloses:
during the sensing operation, a reference voltage is applied to the selected word line and pass voltages are applied to a plurality of unselected word lines (para. [0126]: “the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation. . . the unselected memory cells are provided with one or more read pass voltages”).
Regarding claim 8, Yang discloses:
A memory device (memory device 100), comprising:
a memory block that includes an array of memory cells that are arranged in a plurality of word lines, a selected word line of a plurality of word lines (FIGs. 6A-6F) being programmed according to a storage scheme that includes at least three data states (FIG. 7B: data states S1-S7);
circuitry for reading the data of the selected word line (FIG. 24), the circuitry being configured to;
during a sensing operation, for a set duration, discharge a sensing capacitor through a selected NAND string that includes a selected memory cell to be read (FIG. 26: step 2605),
after discharging the sensing capacitor for the set duration, conduct a first comparison of a voltage at a sense node to a trip voltage (FIG. 26: step 2607), and
apply a first voltage to an opposite side of the sensing capacitor from the sense node, and then conduct a second comparison of the voltage at the sense node to the trip voltage (FIG. 26: step 2611).
Regarding claim 14, Yang discloses:
during the sensing operation, the circuitry applies a reference voltage to the selected word line and pass voltages to a plurality of unselected word lines (para. [0126]: “the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation. . . the unselected memory cells are provided with one or more read pass voltages”).
Regarding claim 15, Yang discloses:
A computing system (para. [0119]: “A processor may also be implemented as a combination of computing devices . . .”), comprising:
a processing unit (para. [0119]);
a plurality of memory packages in electrical communication with the processing unit (para. [0119]: “The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general-purpose processor . . .”);
each of the memory packages including at least one memory block that includes an array of memory cells that are arranged in a plurality of word lines, a selected word line of a plurality of word lines (FIGs. 6A-6F) being programmed according to a storage scheme that includes at least three data states (FIG. 7B: data states S1-S7); and
each of the memory packages including sensing circuitry for reading the data of the selected word line (FIG. 24), the sensing circuitry being configured to;
during a sensing operation, for a set duration, discharge a sensing capacitor through a selected NAND string that includes a selected memory cell to be read (FIG. 26: step 2605),
after discharging the sensing capacitor for the set duration, conduct a first comparison of a voltage at a sense node to a trip voltage (FIG. 26: step 2607), and
apply a first voltage to an opposite side of the sensing capacitor from the sense node, and then conduct a second comparison of the voltage at the sense node to the trip voltage (FIG. 26: step 2611).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 9, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20220383965 A1; hereinafter "Yang") in view of Sforzin et al (US 20240062824 A1; hereinafter "Storzin").
Regarding claims 2, 9, and 16, Yang discloses the elements of claims 1, 8, and 15, respectively, as set forth in the anticipation rejections above.
Yang discloses multilevel memory cells (MLC) but does not disclose a storage scheme including only three data states including a first data state, a second data state, and a third data state.
Sforzin, in the same field of endeavor discloses three data states (Abstract and FIG. 3A).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the multilevel memory cells of Yang to include only three data states, as disclosed by Sforzin, because multilevel memory cells were known in the art to include three or more data states.
Claim(s) 4, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20220383965 A1; hereinafter "Yang") in view of Choi (US 11990191 B2).
Regarding claims 4, 11, and 18, Yang discloses the elements of claims 1, 8, and 15, respectively, as set forth in the anticipation rejections above.
Yang discloses multilevel memory cells (MLC) but does not disclose a storage scheme including only four data states including a first data state, a second data state, a third data state, and a fourth data state.
Choi, in the same field of endeavor discloses four data states (para. [0139] and FIG. 7).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the multilevel memory cells of Yang to include only four data states, as disclosed by Choi, because multilevel memory cells were known in the art to include three or more data states.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 8, and 15 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,532,370. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of U.S. Patent No. 11,532,370 discloses, a memory device comprising a control circuit configured to connect to an array of non-volatile memory cells, wherein claim 1 teaches the control circuit is configured to:
during a sensing operation, for a set duration, discharge a sensing capacitor through a selected NAND string that includes a selected memory cell to be read (“discharge the first plate of the sensing capacitor through the selected memory cell for a sensing interval and trap a resultant charge level on the first plate of the sensing capacitor”),
after discharging the sensing capacitor for the set duration, conduct a first comparison of a voltage at a sense node to a trip voltage (“verify a first threshold voltage level for the selected memory cell by discharging a data latch node by an amount dependent the resultant trapped charge level on the first plate of the sensing capacitor when a second plate of the sensing capacitor is at a first voltage level”), and
apply a first voltage to an opposite side of the sensing capacitor from the sense node, and then conduct a second comparison of the voltage at the sense node to the trip voltage (“verify a second threshold voltage level for the selected memory cell by discharging the data latch node by an amount dependent the resultant trapped charge level on the first plate of the sensing capacitor when the second plate of the sensing capacitor is at a second voltage level that is higher than the first voltage level”).
Claims 2, 9, and 16 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,532,370 in view of Sforzin et al. (US 20240062824 A1). Multilevel memory cells were known at the time of the invention to include three or more data states.
Claims 4, 11, and 18 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,532,370 in view of Choi (US 11990191 B2). Multilevel memory cells were known at the time of the invention to include three or more data states.
Allowable Subject Matter
Claims 3, 5-6, 10, 12-13, 17, and 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
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/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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