DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 6 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-8, 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (PGPUB 20230386543), hereinafter as Tran.
Regarding claim 1, Tran teaches an apparatus comprising: a cross-point array (Fig 9A) comprising a plurality of first conductive lines, a plurality of second conductive lines, and programmable resistance memory cells (Fig 9A, each cell comprising a switching element and a resistive element); and one or more control circuits (Fig 2A, control circuits) in communication with the cross-point array, wherein the one or more control circuits are configured to:
identify a first group of programmable resistance memory cells in the cross- point array for a forming operation, wherein each programmable resistance memory cell in the first group is connected between a first conductive line of the plurality of first conductive lines and a second conductive line of the plurality of second conductive lines that are not connected to any other memory cell in the first group (Fig 22, the cells selected for a ECC codeword are not connected to each other, refresh the group, it is well known that refreshing including a writing/forming step e.g. Kawamura PGPUB 20170192903 [0153]); and
apply at least one forming signal to each programmable resistance memory cell in the first group during a first period of time in which no forming signal is applied to any other programmable resistance memory cell in the cross-point array ([0188] selector refresh…in parallel on a group, ….the same group may undergo memory element refresh in parallel; and it is obvious cells not in the group are not refreshed).
Regarding claim 2, Tran teaches to: i) identify a second group of programmable resistance memory cells in the cross-point array for the forming operation after performing the forming operation on all memory cells in the first group, wherein each programmable resistance memory cell in the second group is connected between a first conductive line and a second conductive line that are not connected to any other memory cell in the second group; ii) apply at least one forming signal to each programmable resistance memory cell in the second group during a second period of time in which no forming signal is applied to any other programmable resistance memory cell in the cross-point array; and iii) repeat said i) and said ii) on a group-by-group basis during additional time periods until the forming operation has been performed on all memory cells in the cross-point array (argument used in rejection of claim applies, and applied the method again to another group is not patentable since mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8).
Regarding claim 3, Tran teaches each first conductive line is connected to one memory cell in each group (Fig 22).
Regarding claim 4, Tran teaches for each time period each memory cell in the group identified for the forming operation is either fully selected or fully unselected (it is well known that a cell within a refresh group is fulling activated, while cells not in the group are fully unselected).
Regarding claim 5, Tran teaches each group contains "n" memory cells; and the plurality of first conductive lines contains a corresponding "n" conductive lines (Fig 22).
Regarding claim 7, Tran teaches the forming operation lowers a threshold voltage of a threshold switch in each programmable resistance memory cell partially to a final target threshold voltage; and the one or more control circuits are configured to repeat the forming operation for each group until the final target threshold voltage has been reached (Fig. 1 and [0047]).
Regarding claim 8, Tran teaches the memory cells in the first group are arranged in one or more diagonals across the cross-point array (Fig 22).
Regarding claim 10, Tran teaches the programmable resistance memory cells each comprise a threshold switching selector in series with a programmable resistance memory element (Fig 9); and the one or more control circuits perform the forming operation to lower threshold voltages of the threshold switching selectors (Fig 1 and [0047]).
Regarding claim 11, Tran teaches the programmable resistance memory cells each comprise an Ovonic Threshold Switch (OTS)memory element ([0045]); and the forming operation is performed to lower threshold voltages of each OTS (Fig 1 and p0047]).
Regarding claim 12, Tran teaches the programmable resistance memory cells each comprise a ReRAM memory cell (Fig 9a); and the one or more control circuits perform the forming operation to form conductive pathways in the ReRAM memory cell ([0047]).
Claim(s) 9, 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, in view of Navon et al. (PGPUB 20150287459), hereinafter as Navon.
Regarding claim 9, Tran teaches a device as in rejection of claim 1,
But not expressly applying an inhibit voltage for unselected cell,
Navon teaches the one or more control circuits are configured to: i) select a memory cell in the first group for the forming operation; ii) apply at least one forming signal to the selected memory cell in the first group while applying signals to unselected memory cells in the cross-point array to inhibit forming; and iii) repeat said i) and said ii) for all memory cells in the first group prior to applying the forming operation to another group of programmable resistance memory cells in the cross-point array (Fig 5D).
Since Navon and Tran are both from the same field of semiconductor memory device, the purpose disclosed by Navon would have been recognized in the pertinent art of Tran.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use an inhibit voltage as in Navon into the device of Tran for the purpose of managing a writing operation of the memory device.
Regarding claim 13, Tran teaches a method for performing a forming operation in programmable resistance memory cells in a cross-point array having a plurality of word lines and a plurality of bit lines, the method comprising:
a) identifying a group of the programmable resistance memory cells in the cross- point array for which each memory cell in the group is the only memory cell connected to its word line and to its bit line, wherein each programmable resistance memory cell includes a threshold switching device having a threshold voltage at which the threshold switching device turns on (Fig 9a);
b) selecting a memory cell in the identified group for the forming operation ( Fig 22);
c) applying a forming signal to the selected memory cell to lower the threshold voltage of the threshold switching device ([0188] refresh is a forming as argued in rejection of claim 1, and [0047] for lowing threshold) while applying signals to unselected memory cells in the array to inhibit turning on the threshold switching device in the unselected memory cells (Navon teaches inhibit);
d) repeating said b) and said c) until the forming operation has been applied to all memory cells in the identified group (refresh in parallel); and
e) repeating said a) through said d) on a group-by-group basis until the forming operation has been performed on all memory cells in the cross-point array, wherein for each group each memory cell in the group is the only memory cell connected to its word line and to its bit line (argument used in rejection of claim 2 applies).
The reason for combining the references used in rejection of claim 9 applies.
Regarding claim 14, Tran teaches identifying the group of the programmable resistance memory cells in the cross-point array for which each memory cell in the group is the only memory cell connected to its word line and to its bit line comprises: identifying a programmable resistance memory cell for each word line of the plurality of word lines (Fig 22).
Regarding claim 15, Tran teaches identifying the group of the programmable resistance memory cells in the cross-point array for which each memory cell in the group is the only memory cell connected to its word line and to its bit line comprises: identifying a programmable resistance memory cell for each bit line of the plurality of word lines (Fig 22).
Regarding claim 16, Tran teaches identifying the group of the programmable resistance memory cells in the cross-point array for which each memory cell in the group is the only memory cell connected to its word line and to its bit line comprises: identifying programmable resistance memory cell that are arranged in one or more diagonals across the cross-point array (Fig 22).
Regarding claim 17, Tran teaches a system, comprising: a cross-point array comprising a plurality of first conductive lines, a plurality of second conductive lines, and programmable resistance memory cells, each programmable resistance memory cell connected between one of the first conductive lines and one of the second conductive lines, each programmable resistance memory cell having a threshold switch having a threshold voltage at which the threshold switch turns on; and one or more control circuits in communication with the cross-point array, wherein the one or more control circuits are configured to:
a) identify a group of the programmable resistance memory cells in the cross point array for a forming operation, the group contain a memory cell connected to each of the first conductive lines;
b) select a memory cell in the identified group for the forming operation;
c) apply a forming voltage to the selected memory cell to lower a threshold voltage of the threshold switch while applying voltages to unelected memory cell in the cross-point array to inhibit turning on the threshold switches in the unelected memory cells, wherein all unselected memory cells in the group are fully unselected;
d) repeat said b) and said c) during a period of time until the forming operation has been applied to all memory cells in the identified group; and
e) repeat said a) through said d) on a group-by-group basis during other periods of time until the forming operation has been performed on all memory cells in the cross-point array (argument used in rejection of claim 13 applies).
Regarding claim 18, Tran teaches each programmable resistance memory cell comprises a programmable resistance memory element in series with the threshold switch, the threshold switch is a selector (Fig 9).
Regarding claim 19, Tran teaches wherein the one or more one or more control circuits are configured to program the threshold switch in each of the programmable resistance memory cells as a resistance memory element (Fig 9).
Regarding claim 20, Tran teaches the threshold switch in each of the programmable resistance memory cells comprises an Ovonic Threshold Switch (OTS) ([0004]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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/MIN HUANG/ Primary Examiner, Art Unit 2827
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