DETAILED ACTION
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/24/25 has been considered by the examiner.
Drawings
The drawings were received on 2/5/25. These drawings are acceptable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims is/are rejected under 35 U.S.C. 103 as being obvious over US 20230395184 to Caraccio et al.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
As per claim 1 Caraccio et al. substantially teaches the claimed method comprising: receiving counter values indicating a count of available repair resources for addressable portions of a memory device array (Paragraph [0033] log information); storing the counter values as repair flag tokens associated with corresponding portions of the addressable portions of the memory device array (Paragraph [0033] a flag (e.g., a maintenance flag)); and responsive to detecting an error in a first addressable portion of the addressable portions of the memory device array (Paragraph [0033] a target address (e.g., the address of the affected or faulty row)), changing the repair flag token associated with the first addressable portion where the error was detected (Paragraph [0033] ).
Although Caraccio et al. doesn’t explicitly disclose a counter to indicate the available resources, however Caraccio et al does teach log information that keeps track of multiple items such as the address of the faulty row and the ability to communicate the status of the spare rows being exhausted in order to trigger further action. (Paragraph [0033] ) Therefore it would have been obvious to a person having ordinary skill in the art at the time of filing of the present application to have used the log reporting of Caraccio et al. because this would be functionally equivalent to the claimed method.
Claim 19 is the processor-readable storage medium corresponding to the method of claim 1 and is rejected for the same reasoning as claim 1.
As per claim 10, Caraccio et al. substantially teaches the claimed system comprising: a host device (Fig 1 element 103); and a memory device coupled to the host device (Fig 1 element 111), wherein the memory device includes a memory device array and control circuitry (Figure 1 element 110), the control circuitry configured to: receive counter values indicating a count of available repair resources for addressable portions of a memory device array (Paragraph [0033] log information); store the counter values as repair flag tokens associated with respective corresponding portions of the addressable portions of the memory device array (Paragraph [0033] a flag (e.g., a maintenance flag)); and responsive to detecting an error in a first addressable portion of the addressable portions of the memory device array (Paragraph [0033] a target address (e.g., the address of the affected or faulty row)), change the repair flag token associated with the first addressable portion where the error was detected (Paragraph [0033]).
Although Caraccio et al. doesn’t explicitly disclose a counter to indicate the available resources, however Caraccio et al does teach log information that keeps track of multiple items such as the address of the faulty row and the ability to communicate the status of the spare rows being exhausted in order to trigger further action. (Paragraph [0033] ) Therefore it would have been obvious to a person having ordinary skill in the art at the time of filing of the present application to have used the log reporting of Caraccio et al. because the memory system would be functionally equivalent to the claimed memory system.
Allowable Subject Matter
Claims 2-9 11-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20240330133 to Shukla et al. teaches in response to an error count for the respective classified correctable faulty row exceeding a desired threshold value, mapping the respective classified correctable faulty row to an available spare row, storing the mapping of the respective correctable faulty row and the mapped spare row in a row repair translation table, and copying data stored in the respective correctable faulty row into the mapped spare row.
US 20240029813 to McCombs, Jr. et al. teaches to locate memory identification of the memory and pointing to a row in the memory for repair and further to update a repair chain in a reuse table with the memory identification that points to the row in the memory for repair, and then update memory status of the memory as ready for use.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA H BRITT whose telephone number is (571)272-3815. The examiner can normally be reached Monday - Thursday 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CYNTHIA H. BRITT
Primary Examiner
Art Unit 2111
/CYNTHIA BRITT/Primary Examiner, Art Unit 2111
Prosecution Insights