DETAILED ACTION
This non-final action is responsive to communications: application filed on 02/05/2025.
Claims 1-20 are pending. Claims 1, 9, and 14 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic DIV priority details.
Information Disclosure Statement
5. IDS filed on 02/05/2025 has been considered.
Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
10. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2020/0371157 A1).
Regarding independent claim 1, Choi teaches a method (method of testing and packaging construction of Fig. 8A: 800 semiconductor memory device. See Fig. 1-Fig. 13 for illustrated components and functionality. See para [0005]-para [0010]), comprising:
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providing a first semiconductor die (Fig. 8A: 200_a4 “dies”) comprising a set of one or more memory arrays (Fig. 3: memory array in 230. See Fig. 8A: array in semiconductor device),
a set of one or more first contacts (Fig. 8A: set of “conductive pads” associated with TSVs. See Fig. 7B: 701, 702; para [0071]), and a set of one or more second contacts (Fig. 8A: 210 “test pads”);
evaluating operations (wafer level die test operation) of the first semiconductor die (Fig. 8A: 200_a4) based at least in part on contacting the set of one or more second contacts (Fig. 8A: 210 “test pads”) with an evaluation probe (para [0029]: “tester” is connected to test pads to perform wafer level die testing); and
coupling the first semiconductor die (Fig. 8A: 200_a4) with a second semiconductor die (Fig. 8A: 200_a3 assumed tested good die) based at least in part on evaluating the operations of the first semiconductor die (in context of para [0029]-para [0032]: in packaging process, tested good die “defect” free identified at wafer level is assembled connected to another good die via TSV and “conductive pads” associated with TSVs),
wherein the coupling (coupling via TSV during stacked packaging) comprises establishing a communicative coupling between each first contact of the set of one or more first contacts (Fig. 8A: 200_a4) with a respective contact of the second semiconductor die (Fig. 8A: 200_a3. See Fig. 8A in context of para [0071], para [0072], para [0073]. See para [0005]-para [0010]; para [0029]-para [0032]).
Regarding claim 2, Choi teaches the method of claim 1, further comprising: providing power to the first semiconductor die via a first subset of the set of one or more second contacts (Fig. 8A in context of para [0034], para [0035], para [0038]: TEST_EN signal supplies power to 230. See pin within 210), wherein the evaluating is based at least in part on the provided power (testing is performed when TEST_EN is active high).
Regarding claim 3, Choi teaches the method of claim 1, further comprising:
providing commands to access at least one memory array of the set of one or more memory arrays of the first semiconductor die via a second subset of the set of one or more second contacts (Fig. 1, Fig. 8A in context of para [0034]: test operation signals from tester sent via 201),
wherein the evaluating is based at least in part on the commands to access the at least one memory array of the set of one or more memory arrays (Fig. 1, Fig. 8A in context of para [0034]: wafer level test probe operation is done by tester and associated test signals).
Regarding claim 4, Choi teaches the method of claim 3, further comprising: providing the commands (para [0034]: test signals) to access the at least one memory array of the set of one or more memory arrays to evaluation interface circuitry (Fig. 2: 220 test circuit) of the first semiconductor die (Fig. 2: 230).
Regarding claim 5, Choi teaches the method of claim 1, further comprising:
providing the first semiconductor die comprising a second set of one or more first contacts (for example channel specific TSVs and associated contacts. See Fig. 13); and
coupling the first semiconductor die (Fig. 8A: 200_a4) with a third semiconductor die (Fig. 8A: 200_a2),
wherein the coupling comprises establishing a second communicative coupling between each first contact of the second set of one or more first contacts with a respective contact of the third semiconductor die (for example channel specific TSVs and associated contacts are coupled between the two dies. See Fig. 13).
Regarding claim 6, Choi teaches the method of claim 1, further comprising: providing the second semiconductor die comprising a second set of one or more memory arrays (Fig. 8A: 200_a3 with semiconductor device, array).
Regarding claim 7, Choi teaches the method of claim 1, wherein: at least a subset of the set of one or more first contacts are coupled with a first data bus of the first semiconductor die (para [0077]: /O channel and associated bus connects buffer die to TSVs); and
at least a subset of the set of one or more second contacts are coupled with one or more second data buses of the first semiconductor die (Fig. 11: data inputs 1114 are connected to 201 test pads).
Regarding claim 8, Choi teaches the method of claim 1, further comprising: providing commands to activate one or more buffers (Fig. 11: 1112, 1116) between a first data bus (Fig. 2-Fig. 11: TEST_EN or IDA_EN signal bus) and one or more second data buses (Fig. 2-Fig. 11: test pad to test circuit connecting bus bus),
wherein the evaluating is based at least in part on the commands to activate the one or more buffers (see Fig. 11: 1112, 1116 are required to be functional for testing).
Regarding independent claim 9, Choi teaches a method (method of testing and packaging/ constructing Fig. 8A: 800 packaged semiconductor device. Para [0072 method of testing and packaging construction of Fig. 8A: 800 semiconductor memory device. See Fig. 1-Fig. 13 for illustrated components and functionality. See para [0005]-para [0010]; para [0072]), comprising:
providing a first semiconductor die (Fig. 8A: 200_a4 “dies”) comprising a set of one or more memory arrays (Fig. 3: memory array in 230. See Fig. 8A: array in semiconductor device),
a set of one or more first contacts (Fig. 8A: set of “conductive pads” associated with TSVs. See Fig. 7B: 701, 702; para [0071]), and a set of one or more second contacts (Fig. 8A: 210 “test pads”),
wherein the set of one or more second contacts are electrically isolated from the set of one or more first contacts (See Fig. 8A, Fig. 7a, Fig. 7B);
evaluating operations (wafer level die test probe operation) of the first semiconductor die (Fig. 8A: 200_a4) based at least in part on the set of one or more second contacts (Fig. 8A: 210 “test pads”) being electrically isolated from the set of one or more first contacts (Fig. 8A: set of “conductive pads” associated with TSVs. Wafer level die test/ probe operation is possible when these conductive pads are isolated allowing wafer level die testing/ probe operation via 210 “test pads” and tester); and
coupling the first semiconductor die (Fig. 8A: 200_a4) with a second semiconductor die (Fig. 8A: 200_a3 assumed tested wafer level good die) based at least in part on evaluating the operations of the first semiconductor die (in context of para [0029]-para [0032]: in packaging process, tested good die “defect” free identified at wafer level is assembled connected to another good die via TSV and “conductive pads” associated with TSVs),
wherein the coupling (coupling via TSV during stacked packaging) comprises establishing a communicative coupling between each first contact of the set of one or more first contacts (Fig. 8A: TSV contacts of 200_a4) with a respective contact of the second semiconductor die (Fig. 8A: TSV contacts of 200_a3. See para [0005]-para [0010]; para [0029]-para [0032]).
Regarding claim 10, Choi teaches the method of claim 9, further comprising:
providing commands (test signals) to activate one or more buffers between a first data bus and one or more second data buses (Fig. 11: 1112, 1116 inside test circuit located between array data input lines and tester data input bus),
wherein the set of one or more first contacts is electrically isolated (not active during wafer level die testing) from the set of one or more second contacts based at least in part on the commands to activate the one or more buffers (Fig. 11: test signals make 1112, 1116 to function).
Regarding claim 11, Choi teaches the method of claim 9, wherein evaluating the operations of the first semiconductor die comprises:
evaluating the operations of the first semiconductor die based at least in part on contacting the set of one or more second contacts with an evaluation probe (Fig. 1, Fig. 8A in context of para [0006], para [0030]).
Regarding claim 12, Choi teaches the method of claim 9, wherein the set of one or more second contacts are included in a reserved region of the first semiconductor die (See Fig 8A: 210), the reserved region isolated from the set of one or more first contacts (See Fig 8A: 210 are in center region and are isolated by dielectric from the edge TSVs).
Regarding claim 13, Choi teaches the method of claim 9, further comprising: providing power to the first semiconductor die via a first subset of the set of one or more second contacts,
wherein evaluating the operations of the first semiconductor die is based at least in part on providing the power. (See claim 2 rejection analysis)
Regarding independent claim 14, Choi teaches a method (method of testing and packaging construction of Fig. 13: 1300 semiconductor memory device. See Fig. 1-Fig. 13 for illustrated components and functionality. See para [0005]-para [0010]. See Para [0103]), comprising:
providing a first semiconductor die (Fig. 13: 200_a4 die) comprising a set of one or more memory arrays (Fig. 13: arrays in semiconductor device. See Fig. 3: memory array),
a set of one or more first contacts (Fig. 13: TSV associated conductive pads connected to 1310, 1320), a set of one or more second contacts (para [0104], Fig. 13: 210 “test pads” associated with CHa), and a set of one or more third contacts (Fig. 13: 210 “test pads” associated with CHb);
evaluating (wafer level die test/ probe operation), via the set of one or more second contacts (para [0104], Fig. 13: 210 “test pads associated with CHa), first operations of the first semiconductor die (para [0029]: “tester” is connected to test pads to perform wafer level CHa testing to identify defect free die and channel);
coupling the first semiconductor die (Fig. 8A: 200_a4 die) with a second semiconductor die (Fig. 8A: 200_a3 die assumed tested good die) based at least in part (taken as partial condition) on evaluating the first operations (CHa testing) of the
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first semiconductor die (in context of para [0029]-para [0032]: in packaging process, tested good die at wafer level is assembled connected to another good die via TSV),
wherein the coupling (Fig. 13: coupling via TSV during stacked packaging) comprises establishing a communicative coupling between each first contact of the set of one or more first contacts (Fig. 8A: TSV and associated conductive pads of 200_a4 die) with a respective contact of the second semiconductor die (Fig. 8A: TSV and associated conductive pads of 200_a3 die); and
evaluating (testing for defect in all channels), via the set of one or more third contacts, second operations of the first semiconductor die (Fig. 13: evaluating CHb operation using 210 “test pads” associated with CHb. Claim language does not describe the limitation in association with particular sequence step and thus the limitation is satisfied).
Regarding claim 15, Choi teaches the method of claim 14, wherein evaluating the second operations of the first semiconductor die comprises:
evaluating the second operations (Fig. 13: CHb operations) of the first semiconductor die (Fig. 13: 200_a4) based at least in part on contacting the set of one or more third contacts (Fig. 13: 210 with CHb) with an evaluation probe (para [0029]: “tester” is connected to test pads to perform wafer level die/ channel testing).
Regarding claim 16, Choi teaches the method of claim 14, wherein evaluating the first operations of the first semiconductor die comprises:
evaluating the first operations (Fig. 13: CHb operations) of the first semiconductor die (Fig. 13: 200_a4) based at least in part on contacting the set of one or more second contacts (Fig. 13: 210 with CHa) with an evaluation probe (para [0029]: “tester” is connected to test pads to perform wafer level die/ channel testing).
Regarding claim 17, Choi teaches the method of claim 14, wherein the coupling renders the set of one or more second contacts physically inaccessible (after packaging, test pad are not accessible and not used) and wherein evaluating the second operations of the first semiconductor die via the set of one or more third contacts is based least in part on the set of one or more second contacts being physically inaccessible (Fig. 13: functional conditions and biasing scheme are directed to channel specific testing).
Regarding claim 18, Choi teaches the method of claim 14, further comprising: providing power to the first semiconductor die via a first subset of the set of one or more second contacts, wherein the evaluating is based at least in part on the provided power (Fig. 13: TEST_EN signal provides power to each die for testing).
Regarding claim 19, Choi teaches the method of claim 14, further comprising:
providing, to evaluation interface circuitry (Fig. 13: 220) of the first semiconductor die (Fig. 13: 200_a4), commands (Test signals from tester) to access at least one memory array of the set of one or more memory arrays of the first semiconductor die (Fig. 13: 200_a4) via a second subset of the set of one or more second contacts (Fig. 13: 210),
wherein the evaluating is based at least in part on the commands (Test signals from tester) to access the at least one memory array of the set of one or more memory arrays (para [0006]).
Regarding claim 20, Choi teaches the method of claim 14, further comprising:
providing commands to activate one or more buffers between a first data bus and one or more second data buses,
wherein the evaluating is based at least in part on the commands to activate the one or more buffers. (See claim 8 rejection analysis)
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Youn et al. (US 2011/0037158A1) is applicable for all claims. Youn teaches an apparatus (Fig. 1A: MCP), comprising: a set of one or more memory arrays of a first memory die (Fig. 1A: 10 “memory chip” with arrays); a set of one or more first contacts (Fig. 1A in context of para [0048], para [0050]: “chip terminals” or pins ALE, CLE, nWP, IO0…IO7) of the first memory die (Fig. 1A: 10) that are configured for communicative coupling with a set of one or more contacts (see Fig. 1A) of a second memory die (Fig. 1A: 12 “memory chip” and “chip terminals” or pins connected), at least a subset of the set of one or more first contacts (Fig. 1A: IO0…IO7) coupled with a first data bus (E.g., data bus portion associated with data output) of the first memory die (Fig. 1A: 10); and a set of one or more second contacts (Fig. 1A in context of para [0048], para [0050]: “chip terminals” or pins nCE1, nCE2, R/B1, RB2) of the first memory die (Fig. 1A: 10) that are configured for testing operations of the first memory die (chip enable signal used in chip specific testing),
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wherein the testing operations occur before the communicative coupling of the set of one or more first contacts of the first memory die with the set of one or more contacts of the second memory die (chip specific testing is done to screen defect using external tester. Testing is done before normal operation and when chip terminals” or pins associated with ALE, CLE, nWP, IO0…IO7 are used) at least a subset of the set of one or more second contacts (Fig. 1A: R/B1, R/B2) coupled with one or more second data buses (E.g., data bus portion associated with data input or, data writing and when device is busy uses R/B signal) of the first memory die (Fig. 10), and wherein the set of one or more second contacts (Fig. 1A: “chip terminals” or pins nCE1, nCE2, R/B1, R/B2 of chip 10) of the first memory die is electrically isolated (see Fig. 1A) from circuitry of the second memory die (Fig. 1A: 12).
Cariello (US 2021/0286904 A1): Cariello teaches an apparatus (Fig. 4: 400 memory system), comprising: a set of one or more memory arrays of a first memory die (Fig. 4: 415-a memory die); a set of one or more first contacts of the first memory die that are configured for communicative coupling with a set of one or more contacts of a second memory die (Fig. 4 in context of para [0057] and para [0043]: teaching of three-dimensional memory array where 415-b is stacked on 415-a implies that the dies are connected via inter-die contacts and again coupled to “…common bus…bus 430…”), at least a subset of the one or more first contacts (suggested Fig. 4: inter-die contacts) coupled with a first data bus of the first memory die (Fig. 4: 480 bus); and
a set of one or more second contacts (Fig. 4: 420-a and 435 pads) of the first memory die (Fig. 4: 415-a) that are configured for testing operations of the first memory die (In context of para [0058], para [0060], para [0063], para [0065]: “selection” and “diagnostic” operation performed using these contacts), at least a subset of the one or more second contacts (Fig. 4: 435) coupled with one or more second data buses of the first memory die (Fig. 4: bus connected to 425 and 405), wherein the testing operations occur before the communicative coupling of the set of one or more first contacts of the first memory die with the set of one or more contacts of the second memory die (Limitation is very broad and treated using Cariello’s diagnosis mode and normal mode. Considering normal operation 1 [Wingdings font/0xE0] verify and diagnosis [Wingdings font/0xE0] normal operation 2: diagnosis or test can happen before normal operation), wherein the set of one or more second contacts (Fig. 4: 420-a and 435 pads) of the first memory die (Fig. 4: 415-a) is electrically isolated from circuitry of the second memory die (Fi. 4 Mux’s act to perform isolation. Fig. 4: 475-b taken as circuitry of the second memory die. Fig. 4 in context of para [0071]: when 415-b is not selected, 435, 420-a are isolated from 475-b. See “…each multiplexer 465 may be configured to isolate the unselected conductive path …conductive path 455 or conductive path 460… from conductive path 475 based on the value stored in register 470…”).
Chibvongodze et al. (US 2020/0365210 A1) is applicable for all claims.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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