Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1 – 20 are presented for examination.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 120 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/11/2025 and 02/18/2025 were received. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 12 objected to because of the following informalities:
“thereron” should be --thereon--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, the limitation “higher than” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of what is compared.
Any claim not addressed above is rejected due to its dependency on a rejected claim
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 – 20 are rejected on the ground of nonstatutory double patenting over claims 1- 10 and 19 of U.S. Patent No. 12,224,771 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 19/047393
Claim 1 – Patent 12,224,771
A device, comprising:
A device, comprising:
an array of non-volatile memory cells; and
an array of non-volatile memory cells; and
a logic circuit configured to:
a logic circuit configured to:
determine a condition of the non-volatile memory cells;
determine a condition of storing a set of data in the non-volatile memory cells for retrieval;
select, based on the condition, a mode of operation of the non-volatile memory cells;
select, based on the condition, a level of redundancy configured to protect the set of data via error correction techniques;
generate, based on the level selected for the condition, redundant data; and
store, using the mode of operation, a set of data in the non-volatile memory cells.
store, in the non-volatile memory cells, the set of data and the redundant data.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 19/047393 is an obvious variation of the claimed subject matter of independent claim 1, of patent 12,224,771. Specifically, both claim 1, of the current application 19/047393, and claim 1, of patent 12,224,771 discloses: A device, comprising: “an array of non-volatile memory cells”, and “a logic circuit configured to: determine a condition of the non-volatile memory cells”.
One of ordinary skill in the art would recognize the device disclosed by claim 1, of the current application 19/047393, as a broad recitation of the operations performed by the device disclosed in claim 1 of Patent 12,224,771. A device performing the operations and a device capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the device of claim 1, of the current application 19/047393, as performing the operations of the device of claim 1, of U.S. Patent 12,224,771, and as such are obvious variants of each other.
Claim 2 – Application 19/047393
Claim 1 – Patent 12,224,771
Claim 3 – Application 19/047393
Claim 2 – Patent 12,224,771
Claim 4 – Application 19/047393
Claim 3 – Patent 12,224,771
Claim 5 – Application 19/047393
Claim 4 – Patent 12,224,771
Claim 6 – Application 19/047393
Claim 5 – Patent 12,224,771
Claim 7 – Application 19/047393
Claim 6 – Patent 12,224,771
Claim 8 – Application 19/047393
Claim 7 – Patent 12,224,771
Claim 9 – Application 19/047393
Claim 8 – Patent 12,224,771
Claim 10 – Application 19/047393
Claim 9 – Patent 12,224,771
Claim 11 – Application 19/047393
Claim 1 – Patent 12,224,771
Claim 12 – Application 19/047393
Claim 10 – Patent 12,224,771
Claim 13 – Application 19/047393
Claim 7 – Patent 12,224,771
Claim 14 – Application 19/047393
Claim 2 – Patent 12,224,771
Claim 15 – Application 19/047393
Claim 10 – Patent 12,224,771
Claim 16 – Application 19/047393
Claim 9 – Patent 12,224,771
Claim 17 – Application 19/047393
Claim 6 – Patent 12,224,771
Claim 18 – Application 19/047393
Claim 10 – Patent 12,224,771
Claim 19 – Application 19/047393
Claim 19 – Patent 12,224,771
Claim 20 – Application 19/047393
Claim 19 – Patent 12,224,771
Claims 1 – 20 are rejected on the ground of nonstatutory double patenting over claims 1, 2, 6, and 7 of U.S. Patent No. 11,870,463 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 19/047393
Claim 1 – Patent 11,870,463
A device, comprising:
A system comprising:
an array of non-volatile memory cells; and
a storage device configured to store data from a host system; and
a logic circuit configured to:
at least one processing device configured to:
determine a condition of the non-volatile memory cells;
obtain a temperature at which the storage device will store the first data;
select, based on the condition, a mode of operation of the non-volatile memory cells;
select a second error correction code based on the obtained temperature; and
store, using the mode of operation, a set of data in the non-volatile memory cells.
store the first portion, the first parity data, the second portion, and the second parity data in the storage device.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 19/047393 is an obvious variation of the claimed subject matter of independent claim 1, of patent 11,870,463. Specifically, both claim 1, of the current application 19/047393, and claim 1, of patent 11,870,463 discloses: the broad concept of using an attribute of the storage array to determine behavior of the system and using that behavior to control storage of data. Patent 11,870,463 specifically, discloses temperature to determine error correction coding. Current application 19/047393 is silent regarding the attribute that is used to select a mode for storage.
One of ordinary skill in the art would recognize the device disclosed by claim 1, of the current application 19/047393, as a very broad recitation of the operations performed by the system disclosed in claim 1 of Patent 11,870,463. A system performing the operations and a device capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the device claim 1, of the current application 19/047393, as performing the operations of the system of claim 1, of U.S. Patent 11,870,463, and as such are obvious variants of each other.
Claim 2 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 3 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 4 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 5 – Application 19/047393
Claim 2 – Patent 11,870,463
Claim 6 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 7 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 8 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 9 – Application 19/047393
Claim 6 – Patent 11,870,463
Claim 10 – Application 19/047393
Claim 6 – Patent 11,870,463
Claim 11 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 12 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 13 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 14 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 15 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 16 – Application 19/047393
Claim 7 – Patent 11,870,463
Claim 17 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 18 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 19 – Application 19/047393
Claim 1 – Patent 11,870,463
Claim 20 – Application 19/047393
Claim 1 – Patent 11,870,463
Claims 1 – 20 are rejected on the ground of nonstatutory double patenting over claims 10, 11, 14, and 18 of U.S. Patent No. 11,296,729 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 19/047393
Claim 10 – Patent 11,296,729
A device, comprising:
A system comprising:
an array of non-volatile memory cells; and
a storage device configured to store data from a host system; and
a logic circuit configured to:
at least one processing device configured to:
determine a condition of the non-volatile memory cells;
determine at least one of a temperature at which the storage device will store the first data, or a time duration during which the storage device will store the first data;
select, based on the condition, a mode of operation of the non-volatile memory cells;
identify at least a first portion of the first data that is to be stored in a part of the storage device susceptible to the determined temperature or the determined time duration; encode the first portion of the first data using a second error correction code to generate second parity data, wherein the second error correction code has a higher error correction capability than the first error correction code; and
store, using the mode of operation, a set of data in the non-volatile memory cells.
store the first portion, the first parity data, and the second parity data in the storage device.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 19/047393 is an obvious variation of the claimed subject matter of independent claim 10, of patent 11,296,729. Specifically, both claim 1, of the current application 19/047393, and claim 10, of patent 11,296,729 discloses: the broad concept of using an attribute of the storage array to determine behavior of the system and using that behavior to control storage of data. Patent 11,296,729 specifically, discloses temperature to determine error correction coding. Current application 19/047393 is silent regarding the attribute that is used to select a mode for storage.
One of ordinary skill in the art would recognize the device disclosed by claim 1, of the current application 19/047393, as a very broad recitation of the operations performed by the system disclosed in claim 10 of Patent 11,296,729. A system performing operations and a device capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the device of claim 1, of the current application 19/047393, as performing the operations of the system of claim 10, of U.S. Patent 11,296,729, and as such are obvious variants of each other.
Claim 2 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim 3 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim 4 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim 5 – Application 19/047393
Claim 11 – Patent 11,296,729
Claim 6 – Application 19/047393
Claim 18 – Patent 11,296,729
Claim 7 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim 8 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim 9 – Application 19/047393
Claim 14 – Patent 11,296,729
Claim 10 – Application 19/047393
Claim 14 – Patent 11,296,729
Claim 11 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim 12 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim 13 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim 14 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim 15 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim 16 – Application 19/047393
Claim 14 – Patent 11,296,729
Claim 17 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim 18 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim 19 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim 20 – Application 19/047393
Claim 10 – Patent 11,296,729
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Achtenberg et al., U.S. Publication 2018/0374548 (herein Achtenberg).
Regarding claim 1, Hemink discloses: A device (figure 2, element 100), comprising: an array of non-volatile memory cells (figure 2, element 126); and a logic circuit configured to: determine a condition of the non-volatile memory cells (figure 11, element 1102, 1104); select, based on the condition, a mode of operation of the non-volatile memory cells (figure 11, element 1104); store, using the mode of operation, a set of data in the non-volatile memory cells (figure 11, element 1108; paragraph 0116, 0118).
Regarding claim 2, Hemink discloses: the logic circuit is further configured to, based on the mode of operation, store redundant data in the non-volatile memory cells (paragraph 0077).
Regarding claim 3, Hemink discloses: the redundant data comprises parity data (paragraph 0077).
Regarding claim 4, Hemink discloses: the condition comprises a temperature paragraph 0116, 0118).
Regarding claim 5, Hemink discloses: the condition comprises a level of processing power used to decode data in the non-volatile memory cells using a given error correction technique (paragraph 0029).
Regarding claim 6, Hemink discloses: the condition comprises a condition of a power supply that supplies power to the non-volatile memory cells (paragraph 0029).
Regarding claim 7, Hemink discloses: the logic circuit is configured to generate redundant data at a first predetermined level and a second predetermined level higher than the first predetermined level (figure 11, element 1106, 1114).
Regarding claim 8, Hemink discloses: the logic circuit is configured to generate first parity data from first data to protect the first data at the first predetermined level, and generate the first parity data and second parity data from the first data to protect the first data at the second predetermined level.
Regarding claim 9, Hemink discloses: the condition is determined based on a machine learning model and sensor data (paragraph 0096, 0097).
Regarding claim 10, Hemink discloses: a sensor configured to generate inputs to the machine learning model to generate a prediction indicative of the condition (paragraph 0096, 0097).
Regarding claim 11, Hemink discloses: the determination of the condition of the non- volatile memory cells comprises a determination of a condition of storing the set of data in the non-volatile memory cells (figure 11).
Regarding claim 12, Hemink discloses: A non-transitory computer storage medium having instructions stored thereon that, upon execution by a computing device, cause the computing device to: determine a predicted condition associated with operation of non-volatile memory cells (figure 11, element 1102, 1104); select, based on the predicted condition, a mode of operation of the non- volatile memory cells (figure 11, element 1104); store, using the mode of operation, a set of data in the non-volatile memory cells (figure 11, element 1108; paragraph 0116, 0118).
Regarding claim 13, Hemink discloses: the mode of operation comprises a level of redundancy at which the set of data is stored in the non-volatile memory cells (paragraph 0077).
Regarding claim 14, Hemink discloses: the mode of operation comprises an error correction technique (paragraph 0077).
Regarding claim 15, Hemink discloses: storage of the set of data in the non-volatile memory cells comprises storage of both the set of data and redundant data in the non-volatile memory cells (paragraph 0077).
Regarding claim 16, Hemink discloses: storage of the redundant data in the non-volatile memory cells occurs based on the mode of operation selected based on the predicted condition (figure 11, element 1108; paragraph 0116, 0118).
Regarding claim 17, Hemink discloses: generate at least one set of redundant data based on the set of data and the mode of operation selected (paragraph 0077).
Regarding claim 18, Hemink discloses: store the at least one set of redundant data in the non-volatile memory cells based on the mode of operation selected (figure 11, element 1108).
Regarding claim 19, Hemink discloses: A method comprising: determining, by a computing device, a condition associated with operating non- volatile memory cells (figure 11, element 1102, 1104); selecting, by the computing device based on the condition, a mode of operation used to store data in the non-volatile memory cells (figure 11, element 1104); storing, by the computing device using the mode of operation, a set of data in the non-volatile memory cells (figure 11, element 1108; paragraph 0116, 0118).
Regarding claim 20, Hemink discloses: generating, by the computing device based on the mode of operation, redundant data based on the set of data (paragraph 0077); and storing, by the computing device in the non-volatile memory cells, the redundant data (paragraph 0077).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hemink; Gerrit Jan et al. US 20150043281 A1
determine a condition of the non-volatile memory cells;
select, based on the condition, a mode of operation of the non-volatile memory cells;
store, using the mode of operation, a set of data in the non-volatile memory cells.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111
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