DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 22 – 41 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 22, 28 – 32, 34, and 37 – 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 9,430,434 (hereinafter Lo) in view of US Patent No. 10,606,713 (hereinafter Kim).
As per claims 22 and 32, Lo teaches an integrated circuit memory component comprising: a first storage (Lo; Figure 8 Item 312a, Claim 6) corresponding to a first memory channel (Lo; Figure 8 Item 702); a second storage (Lo; Figure 8 Item 312b, Claim 6) corresponding to a second memory channel (Lo; Figure 8 Item 704); and data input/output (I/O) circuitry (Lo; Figure 8 Items 110a and 110b) having first and second data interfaces (Lo; Figure 8 Items 114) and being operable in: a first IO mode in which the first and second data interfaces are dedicated to the first and second memory channels, respectively, such that the first data interface conveys data exclusively with respect to the first storage and the second data interface conveys data exclusively with respect to the second storage (Lo; Figure 9, Col 5 Line 65 – Col 6 Line 29), and a second IO mode in which the first data interface conveys data with respect to both the first storage and the second storage while the second data interface is disabled (Lo; Figure 10, Col 5 Line 65 – Col 6 Line 29).
Lo does not explicitly teach the first and second storage being a first and second plurality of storage banks.
However, Kim teaches a memory system comprising a first plurality of storage banks (Kim; Figure 1 Item 102A) corresponding to a first memory channel (Kim; Figure 210A) and a second plurality of storage banks (Kim; Figure 1 Item 102B) corresponding to a second memory channel (Kim; Figure 1 Item 210B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Lo to include the storage banks because memory arranged in storage banks is a well-known memory architecture in DRAM memory (Kim; Col 5 Lines 4 – 21).
As per claims 28 and 37, Kim also teaches wherein the first plurality of storage banks comprises N storage banks and the second plurality of storage banks also comprises N storage banks such that, while the data IO circuitry is operable in the second IO mode, the first data interface conveys data to or from any one or more of 2*N storage banks (Kim; Col 10 Lines 13 – 36).
As per claims 29 and 38, Kim also teaches first and second command/address interfaces (Kim; Figure 1 Items 210A and 201B, Col 6 Lines 13 – 17) corresponding to the first and second memory channels, respectively, the first command/address interface to receive (i) first memory read and write commands that instruct memory read and write operations exclusively within the first plurality of storage banks while the data IO circuitry is operable in the first IO mode (Kim; Col 6 Lines 39 – 58, Col 7 Lines 8 – 16), and (ii) second memory read and write commands that instruct memory read and write operations within any constituent storage banks of the first and second pluralities of storage banks while the data IO circuitry is operable in the second IO mode (Kim; Col 7 Lines 16 – 27).
As per claims 30 and 39, Lo in combination with Kim also teaches wherein the second command/address interface comprises circuitry to receive third memory read and write commands that instruct memory read and write operations exclusively within the second plurality of storage banks while the data IO circuitry is operable in the first IO mode (Kim; Col 10 Lines 8 – 10), the integrated-circuit memory component further comprising circuitry to disable the second command/address interface while the data IO circuitry is operable in the second IO mode (Lo; Col 5 Line 65 – Col 6 Line 29).
As per claim 31, Lo also teaches wherein the circuitry to disable the second command/address interface comprises circuitry to also disable the second data interface while the data IO circuitry is operable in the second IO mode (Lo; Col 5 Line 65 – Col 6 Line 29).
As per claim 34, Lo also teaches wherein transitioning the data IO circuitry from the first IO mode to the second IO mode comprises receiving a memory access command indicating that first data is to be conveyed via the data IO circuitry and including a field of one or more bits specifying the second IO mode with respect to conveyance of the first data (Lo; Col 4 Lines 19 – 22).
As per claim 40, Lo also teaches after transitioning the data IO circuitry from the first IO mode to the second IO mode, transitioning the data IO circuitry from second IO mode to the first IO mode, including re-enabling the second data interface (Lo; Col 4 Lines 8 – 35).
Claim(s) 23 – 25 and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 9,430,434 (hereinafter Lo) in view of US Patent No. 10,606,713 (hereinafter Kim) and further in view of US Patent No. 9,117,496 (hereinafter Shaeffer).
As per claim 23, Lo in combination with Kim teaches the invention as described per claim 22 (see rejections of claim 22 above).
Lo in combination with Kim does not explicitly teach wherein the data IO circuitry operates in the first IO mode when a mode control value specifies the first IO mode and operates in the second IO mode when the mode control value specifies the second IO mode.
However, Shaefer teaches a memory system in which an IO mode operated according to a mode control value (Shaefer; Col 9 Lines 9 – 18).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Lo in combination with Kim to include the mode control value because doing so allows for dynamically changing IO characteristics of the system.
As per claim 24, Shaefer also teaches a programmable register to store the mode control value (Shaefer; Col 9 Lines 3 – 38).
As per claim 25, Lo also teaches a command/address interface to receive a memory access command that (i) indicates that first data is to be conveyed via the data IO circuitry and (ii) includes, as the mode control value, a field of one or more bits that specify either the first IO mode or the second IO mode with respect to conveyance of the first data (Lo; Col 4 Lines 19 – 22).
As per claim 33, Lo in combination with Kim teaches the invention as described per claim 32 (see rejections of claim 32 above).
Lo in combination with Kim does not explicitly teach wherein transitioning the data IO circuitry from the first IO mode to the second IO mode comprises overwriting, within a programmable register of the integrated-circuit memory component, a first mode control value that specifies the first IO mode with a second mode control value that specifies the second IO mode.
However, Shaefer teaches a memory system in which an IO mode is changed by storing a value in a register (Shaefer; Col 9 Lines 3 – 8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Lo in combination with Kim to include the mode control value because doing so allows for dynamically changing IO characteristics of the system.
Claim(s) 26, 27, 35, and 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 9,430,434 (hereinafter Lo) in view of US Patent No. 10,606,713 (hereinafter Kim) and further in view of US Patent No. 10,671,319 (hereinafter Shin).
As per claims 26 and 35, Lo in combination with Kim teaches the invention as described per claims 22 and 32 (see rejections of claims 22 and 32 above).
Lo in combination with Kim does not explicitly teach wherein each of the storage banks within the first plurality of storage banks and the second plurality of storage banks comprises a respective bank of sense amplifiers and a respective plurality of rows of storage cells coupled to the respective bank of sense amplifiers.
However, Shin teaches a DRAM architecture in which storage banks (Shin; Figure 4 Item 341) comprise a sense amplifier (Shin; Figure 4 Item 343) and a plurality of rows of storage cells (Shin; Col 7 Lines 42 – 50).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Lo in combination with Kim to include the sense amplifier and row of storage cells because doing so is well-known in DRAM memory architecture.
As per claims 27 and 36, Lo in combination with Kim and Shin also teaches wherein each storage cell within the respective plurality of rows of storage cells is a dynamic random access memory (DRAM) cell (Lo; Abstract, Col 6 Lines 3 – 6) (Kim; Col 4 Lines 16 – 51) (Shin; Col 3 Line 64 – Col 4 Line 8).
Claim(s) 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 9,430,434 (hereinafter Lo) in view of US Patent No. 10,606,713 (hereinafter Kim), further in view of US Patent No. 10,671,319 (hereinafter Shin), and further in view of US Patent No. 9,117,496 (hereinafter Shaeffer).
As per claim 41, Lo teaches an integrated circuit memory component comprising: a first storage (Lo; Figure 8 Item 312a, Claim 6) corresponding to a first memory channel (Lo; Figure 8 Item 702); a second storage (Lo; Figure 8 Item 312b, Claim 6) corresponding to a second memory channel (Lo; Figure 8 Item 704); and data input/output (I/O) circuitry (Lo; Figure 8 Items 110a and 110b) having first and second data interfaces (Lo; Figure 8 Items 114) and being operable in: a first IO mode in which the first and second data interfaces are dedicated to the first and second memory channels, respectively, such that the first data interface conveys data exclusively with respect to the first storage and the second data interface conveys data exclusively with respect to the second storage (Lo; Figure 9, Col 5 Line 65 – Col 6 Line 29), and a second IO mode in which the first data interface conveys data with respect to both the first storage and the second storage while the second data interface is disabled (Lo; Figure 10, Col 5 Line 65 – Col 6 Line 29).
Lo does not explicitly teach the first and second storage being a first and second plurality of storage banks; wherein each of the storage banks within the first plurality of storage banks and the second plurality of storage banks comprises a respective bank of sense amplifiers and a respective plurality of rows of storage cells coupled to the respective bank of sense amplifiers; and a programmable register to store an input/output (I/O) mode value.
However, Kim teaches a memory system comprising a first plurality of storage banks (Kim; Figure 1 Item 102A) corresponding to a first memory channel (Kim; Figure 210A) and a second plurality of storage banks (Kim; Figure 1 Item 102B) corresponding to a second memory channel (Kim; Figure 1 Item 210B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Lo to include the storage banks because memory arranged in storage banks is a well-known memory architecture in DRAM memory (Kim; Col 5 Lines 4 – 21).
Lo in combination with Kim does not explicitly teach wherein each of the storage banks within the first plurality of storage banks and the second plurality of storage banks comprises a respective bank of sense amplifiers and a respective plurality of rows of storage cells coupled to the respective bank of sense amplifiers; and a programmable register to store an input/output (I/O) mode value.
However, Shin teaches a DRAM architecture in which storage banks (Shin; Figure 4 Item 341) comprise a sense amplifier (Shin; Figure 4 Item 343) and a plurality of rows of storage cells (Shin; Col 7 Lines 42 – 50).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Lo in combination with Kim to include the sense amplifier and row of storage cells because doing so is well-known in DRAM memory architecture.
Lo in combination with Kim and Shin does not explicitly teach a programmable register to store an input/output (I/O) mode value.
However, Shaefer teaches a programmable register to store an input/output (I/O) mode value (Shaefer; Col 9 Lines 3 – 38).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Lo in combination with Kim and Shin to include the programmable register because doing so allows for dynamically changing IO characteristics of the system.
Conclusion
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/RICHARD B FRANKLIN/ Examiner, Art Unit 2181
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