DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed February 6, 2025.
Claims 1-20 are pending. Claims 1, 8 and 16 are independent.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on February 6, 2025. This IDS has been considered.
Drawings
The drawings are objected to because:
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
Applicant’s Figure 1 is identical to U.S. 10,839,873 Figure 3B.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it contains a phrase that can be implied (i.e. “apparatuses and computing systems are disclosed”). A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4-6, 8-13 and 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 4, 15 and 17-20 of U.S. Patent No. 12,243,580. Although the claims at issue are not identical, they are not patentably distinct from each other because: application claims 1 and 4-5 are anticipated by 12,243,580 claim 1. Claims 6 is anticipated by 12,243,580 claim 2. Claims 8-11 are anticipated by 12,243,580 claim 4. Claims 12-13 are anticipated by 12,243,580 claim 15. Claims 16-17 are anticipated by 12,243,580 claim 17. Claims 18-20 are anticipated by 12,243,580 claims 18-20.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bringivijayaraghavan et al. (U.S. 2020/0342918; hereinafter “Bringivijayaraghavan”).
Regarding independent claim 16, Bringivijayaraghavan discloses a computing system (Fig. 4A), comprising:
control circuitry (Fig. 4A: 490) comprising:
a pull-up sense amplifier comprising P-type fin field effect transistors (FinFETs) (Fig. 2: 243a/243c);
a pull-down sense amplifier comprising N-type FinFETs (Fig. 2: 211a/211b);
global input-output (GIO) lines electrically connected to the pull-up sense amplifier and the pull-down sense amplifier (Fig. 2: 215/225); and
GIO pre-charge circuitry configured to pre-charge the GIO lines to a low power supply voltage potential (see page 2, par. 0009-0010 and page 5, par. 0034).
Regarding claim 17, Bringivijayaraghavan discloses column select gates for electrically coupling the GIO lines to at least one of the pull-up sense amplifier or the pull-down sense amplifier (Fig. 2: 243a-243c, see also page 5, par. 0034).
Regarding claim 18, Bringivijayaraghavan discloses the column select gates include additional P-type FinFETs positioned adjacent at least one of the pull-up sense amplifier or the pull-down sense amplifier (Fig. 2: 243a-243c).
Regarding claim 19, Bringivijayaraghavan discloses wherein the control circuitry is free of threshold voltage potential compensation transistors to compensate for a mismatch between a first threshold voltage potential associated with the P-type FinFETs and a second threshold voltage potential associated with the N-type FinFETs (see page 6, par. 0037).
Regarding claim 20, Bringivijayaraghavan discloses a memory device including the control circuity (Fig. 4A: 400).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Bringivijayaraghavan et al. (U.S. 2020/0342918; hereinafter “Bringivijayaraghavan”) in view of Liu et al. (U.S. 2023/0230633; hereinafter “Liu”).
Regarding independent claim 1, Bringivijayaraghavan teaches an apparatus (Fig. 4A), comprising:
a sense amplifier comprising fin field effect transistors (FinFETs) (Fig. 2: 200, see page 6, par. 0038);
a global input-output (GIO) line electrically connected to the sense amplifier (Fig. 2: 215/225) and
GIO pre-charge circuitry configured to pre-charge the GIO line to a first power supply voltage potential (see page 2, par. 0009-0010 and page 5, par. 0034).
However, Bringivijayaraghavan is silent with respect to a local input/output (LIO) line and LIO circuitry configured to pre-charge the LIO line to a pre-charge voltage potential substantially halfway between the first power supply voltage potential and a second higher power supply voltage potential.
Similar to Bringivijayaraghavan, Liu teaches an apparatus comprising a sense amplifier (Fig. 1: Bit line sense amplifer/Local sense amplifier/Input/output amplifier) and global input-output (GIO) line (Fig. 1: GIO and /GIO).
Furthermore, Liu teaches a local input/output (LIO) line (Fig. 1: LIO and /LIO) and LIO circuitry configured to pre-charge the LIO line to a pre-charge voltage potential substantially halfway between the first power supply voltage potential and a second higher power supply voltage potential (see page 2, par. 0050, pages 3-4, par. 0070-0072 and page 5, par. 0097).
Since Liu and Bringivijayaraghavan are from the same field of endeavor, the teachings described by Liu would have been recognized in the pertinent art of Bringivijayaraghavan.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Liu with the teachings of Bringivijayaraghavan for the purpose of improve a signal transmission speed and reduce a signal transmission delay, see Liu’s page 1, par. 0004.
Regarding claim 2, Bringivijayaraghavan in combination with Liu teaches the limitations with respect to claim 1.
Furthermore, Bringivijayaraghavan teaches a first wafer including the sense amplifier, the GIO line, and the GIO pre-charge circuitry (Fig. 4A: 490).
Regarding claim 3, Bringivijayaraghavan in combination with Liu teaches the limitations with respect to claim 2.
Furthermore, Bringivijayaraghavan teaches a second wafer bonded to the first wafer and including an array of memory cells (Fig. 4A: 481).
Regarding claim 4, Bringivijayaraghavan in combination with Liu teaches the limitations with respect to claim 1.
Furthermore, Bringivijayaraghavan teaches the sense amplifier comprise pull-up circuitry comprising at least one P-type FinFET (Fig. 2: 243a/243c) and pull-down circuitry comprising at least one N-type FinFET (Fig. 2: 211a/211b).
Regarding claim 5, Bringivijayaraghavan in combination with Liu teaches the limitations with respect to claim 1.
Furthermore, Bringivijayaraghavan teaches wherein the GIO line is electrically coupled to the sense amplifier via a column select gate (Fig. 1: 111.1).
Regarding claim 6, Bringivijayaraghavan in combination with Liu teaches the limitations with respect to claim 5.
Furthermore, Bringivijayaraghavan teaches wherein the column select gate comprises a P-type FinFET positioned adjacent a pull-up sense amplifier region of the sense amplifier (Fig. 1: 111.1/112.1).
Allowable Subject Matter
Claims 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 14, there is no teaching or suggestion in the prior art of record to provide the recited FinFET wafer overlays the array wafer.
With respect to claim 15, there is no teaching or suggestion in the prior art of record to provide the recited contact area for electrically connecting the sense amplifier region of the FinFET wafer to one or more digit lines of the array wafer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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