DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 02/06/2025. Claims 1-20 are pending in the Application, of which Claims 1, 8 and 15 are independent.
Continuity/ Priority Information
The present Application 19047534 filed 02/06/2025 is a Continuation of 17937924 , filed 10/04/2022, now U.S. Patent No. 12,242,346.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/06/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (Pub. No. US 20090316474).
Regarding independent Claims 1, 8 and 15, Cho discloses a semiconductor memory device, for example, such as a phase change memory device. comprising:
a memory array including memory cells organized in column planes; [0037] Referring to FIG. 2, the phase change memory device 200 includes a memory cell array 210, a column selector 220, a sense amplifier/write drive circuit 230, a multiplexer 240, a data input/output circuit 250, a row decoder 260, a column decoder 270, a repair control circuit 280 “global column repair circuitry” and a control logic 290.
a number of column decoder circuits (decoder 270), each local column decoder circuit of the number of local column decoder circuits local to an associated column plane; [0046] The column decoder 270 receives a column address CA from an external device (not shown). The column decoder 270 decodes the column address CA, and controls the column selector 220 so that bitlines may be selected in response to the decoded column address DCA. FIG. 3. The column selector 220 electrically connects the redundant global bitlines RGBLR and RGBLW to the sense amplifier/write drive circuit 230 in response to the control signal RS provided from the repair control circuit 280.
global column repair circuitry (repair control circuit 280, shown in Figs. 2, 3 and 5A) coupled to each local column decoder circuit, comprising match circuitry configured to compare a received column address to a number of known defective column addresses; [0047] The repair control circuit 280 also receives column address CA and block address BA from the external device. The repair control circuit 280 stores repair information of the bitlines of the memory cell array 210. When the column address CA and the block address BA transmitted from the external device indicates the repaired bitlines, the repair control circuit 280 activates control signal RS and redundant flag signal RAI. The column selector 220 selects redundant bitlines in response to the activated control signal RS. The multiplexer 240 selects the redundant sense amplifier/write drivers of the sense amplifier/write driver circuit 230, in response to the activated redundant flag signal RAI.
disable a column address driver corresponding to a defective column plane responsive to a determination that the received column address matches a known defective column address; [0083] The compare circuit 2811 receives outputs of the fuse units FM1-FMn. When at least one of the fuses FM1-FMn is cut, the compare circuit 2811 is configured to activate an active signal EN. For example, when at least one of the global bitlines for reading and writing GBLR and GBLW is repaired into redundant global bitlines for reading and writing RGBLR and RGBLW, the compare circuit 2811 is configured to active the active signal EN. In an example embodiment, when an output of at least one of the fuse units FM1-FMn is logic high, the compare circuit 2811 activates the active signal EN.
Regarding Claims 2, 12, Cho discloses latch circuitry configured to store the defective column addresses. FIG. 5A. the master repair circuit 2810 may include a plurality of fuses each corresponding to each of the reading and writing global bitlines GBLR and GBLW. For example, the master repair circuit 2810 stores information on whether the read and writing global bitlines GBLR and GBLW are repaired, depending on whether the plurality of fuses are cut.
Regarding Claims 3, 7, 9, 10, 11, 14, Cho discloses match circuitry; [0118] Referring to FIG. 7, tests are performed on the address groups AG1 of the banks BANK1 to BANKm. The test is performed by performing the reading, writing and erase operations repeatedly. When a defect is detected in the phase change memory cells connected to the local bitlines LBL, or a defect is detected in the local bitlines LBL, the local bitlines LBL are repaired into redundant local bitlines by the repair control circuit 280.
Regarding Claims 4, 5, 16, 19, 20, Cho discloses wherein the global column repair circuitry is configured to disable or enable a column address driver. [0083] The compare circuit 2811 receives outputs of the fuse units FM1-FMn. When at least one of the fuses FM1-FMn is cut, the compare circuit 2811 is configured to activate an active signal EN. For example, when at least one of the global bitlines for reading and writing GBLR and GBLW is repaired into redundant global bitlines for reading and writing RGBLR and RGBLW, the compare circuit 2811 is configured to active the active signal EN.
Regarding Claim 6, Cho discloses a first wafer including the memory array; [0033] Referring to FIG. 1, the memory system 10 according to an example embodiment of the present invention includes a controller 100 and a phase change memory device 200.
Regarding Claim 13, Cho discloses the device further comprising a number of column select gates, [0041] The column selector 220 is connected to the memory cell array 210 via the bitlines. The column selector 220 selects the bitlines in response to a control by the column decoder 270. The column selector 220 selects redundant bitlines in response to control signals transmitted from the repair control circuit 280. The selected bitlines/redundant bitlines are electrically connected to the sense amplifier/write drive circuit 230 via the column selector 220.
Regarding Claims 17-20, Cho discloses defective column address; [0065] if a defect occurs in the memory cells connected to the local bitline LBL, or a defect occurs in the local bitline LBL, the local bitline LBL may be repaired as a redundant local bitline. In another example embodiment, if defect occurs in the global bitlines for reading GBLR or the global bitlines for writing GBLW, the global bitlines for reading and writing GBLR and GBLW may be repaired into redundant global bitlines for reading and writing RGBLR and RGBLW. Information on the repaired local bitline LBL or the repaired global bitlines for reading and writing GBLR and GBLW are stored in the repair control circuit 280.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims1-24 of U.S. Patent No.12,242,346. Although the claims at issue are not identical, they are not patentably distinct from each other because the Claims of the instant Application are broader in scope than the Claims recited in the U.S. Patent No. 12,242,346 , and thus anticipate the Claims of the instant Application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent/application claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of bviousness- type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus).“ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
TABLE A: Double Patenting Claims comparison
19047534 Instant Application Claims
(U.S. Patent No. 12,242,346) Claims
1. A device, comprising:
a memory array including memory cells organized in column planes;
a number of column decoder circuits, each local column decoder circuit of the number of local column decoder circuits local to an associated column plane of the column planes; and
global column repair circuitry coupled to each local column decoder circuit of the number of local column decoder circuits, the global column repair circuitry comprising match circuitry configured to:
compare a received column address indicated by a received column address signal to a number of known defective column addresses; and
disable a column address driver corresponding to a defective column plane responsive to a determination that the received column address matches a known defective column address associated with a defective column plane.
1. An apparatus, comprising:
a memory array including memory cells organized in column planes, the column planes associated with respective column addresses;
local column decoder circuitry including two or more local column decoder circuits, each local column decoder circuit of the two or more local column decoder circuits local to an associated column plane of the column planes, the local column decoder circuitry configured to, if enabled, decode a received column address signal to generate a column select signal; and
global column repair circuitry coupled to each local column decoder circuit of the two or more local column decoder circuits, the global column repair circuitry comprising:
column address drivers corresponding to respective ones of the column planes, the column address drivers configured to, if enabled, drive the received column address signal to the local column decoder circuitry of respective ones of the column planes;
data storage elements configured to store known defective column addresses corresponding to defective column planes; and
match circuitry coupled to each local column decoder circuit of the two or more local column decoder circuits, the match circuitry configured to:
compare a received column address indicated by the received column address signal to the known defective column addresses; and
disable a column address driver corresponding to a defective column plane responsive to a determination that the received column address matches a known defective column address associated with the defective column plane.
8. A device, comprising: a number of local column decoder circuits, each local column decoder circuit of the number of local column decoder circuits local to an associated column plane of a number of column planes; and match circuitry coupled to each local column decoder circuit of the number of local column decoder circuits, the match circuitry configured to disable a column address driver corresponding to a defective column plane responsive to a received column address indicated by a received column address signal matching one of a number of defective column addresses corresponding to the defective column plane.
7. An apparatus, comprising: an array wafer including memory cells organized in column planes; a control circuitry wafer bonded to the array wafer, the control circuitry wafer including: local column decoder circuitry including two or more local column decoder circuits, each local column decoder circuit of the two or more local column decoder circuits local to an associated column plane of the column planes; column address drivers corresponding to respective ones of the column planes, the column address drivers configured to, if enabled, drive a received column address signal to the local column decoder circuitry corresponding to the respective ones of the column planes; data storage elements configured to store known defective column addresses; and match circuitry coupled to each local column decoder circuit of the two or more local column decoder circuits, the match circuitry configured to disable a column address driver corresponding to a defective column plane that corresponds to one of the known defective column addresses responsive to a received column address indicated by the received column address signal matching the one of the known defective column addresses.
15. A method of operating a memory device, the method comprising: receiving a column address at global column repair circuitry; and disabling a local column address driver responsive to a determination that the received column address matches a defective column address that corresponds to a known defective column plane.
13. A method of operating a memory device, the method comprising: determining, by global column repair circuitry that is coupled to a plurality of column planes, whether a received column address indicated by a received column address signal matches a defective column address that corresponds to a known defective column plane; disabling a column address driver corresponding to the known defective column plane responsive to a determination that the received column address matches the defective column address; and enabling a column address driver corresponding to a global column repair plane in place of the column address driver corresponding to the known defective column plane.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: June 24, 2026
Non-Final Rejection 20260624
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
Prosecution Insights