Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claim 1-20 are pending.
Applicant has amended independent claim 1 to further recite: “a first transistor comprising a control electrode connected to a first node, a first electrode connected to, and configured to receive a first power voltage from, a second node, and a second electrode connected to a third node;”
Applicant has noted that in annotated figure of prior art CN 117456905 A from previous office action, the second node as labeled does not provide first power voltage to the first electrode of the first transistor.
Applicant's arguments filed have been fully considered but they are not persuasive.
Examiner respectfully submit that examiner must construe claim terms in the broadest reasonable manner during prosecution as is reasonably allowed in an effort to establish a clear record of what applicant intends to claim. Under a broadest reasonable interpretation, words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. The plain meaning of a term means the ordinary and customary meaning given to the term by those of ordinary skill in the art at the time of the invention (see MPEP 2111).
It is submitted herein that a node may be interpreted as any point at which electrode are connected.
Examiner respectfully submit that adding the feature “configured to receive a first power voltage from the second node” does not distinguish the claim from prior art as the second node in prior art 117456905 may be interpreted / denoted as a point that is “upstream” or “above” from the remaining part of first electrode of the first transistor in relation to first power volage Vdd_PWM, as shown in annotated figures below:
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It is submitted that under this alternative interpretation of “second node” and “first electrode” of the first transistor, the function of pixel circuit as disclosed by prior art is not affected from previous interpretation, and the additional feature of “configured to receive a first power voltage from a second node” is not sufficient to render amended claim allowable over cited prior art. Corresponding prior art rejections have been respectively maintained and updated.
Allowable Subject Matter
Claims 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9, 10, 12, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhong et al., CN 117456905 A (hereinafter “Zhong”).
Regarding claim 1, Zhong discloses a pixel circuit (fig. 10, see annotated figure below) comprising:
a first transistor (fig. 10, transistor Tdr2) comprising a control electrode connected to a first node (fig. 10, node N4), a first electrode connected to, and configured to receive a first power voltage (fig. 10, voltage Vdd_PWM) from, a second node (fig. 10, see annotated second node and first electrode below), and a second electrode connected to a third node (fig. 10, node N5);
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a second transistor (fig. 10, transistor Tc2) connected to the first node (fig. 10 node N4) and the second node (fig. 10, see annotate figure above and below);
a third transistor (fig. 10, transistor Tda2) configured to apply a data voltage (fig. 10, PWDA) to the first transistor;
a seventh transistor (fig. 10, transistor Tdr1) connected to a fourth node (fig. 10, node N1), and configured to apply a driving current to a light-emitting element (fig. 10, light-emitting element Di) ;
a ninth transistor (fig. 10, transistor Ti1) configured to apply a constant-current voltage (fig. 10, VL1) to the fourth node (fig. 10, node N1); and
the light-emitting element configured to emit a light based on the data voltage and the constant-current voltage (see details of pixel circuit operation in paragraph 100-141, in particular, light emitting diode Di emit light controlled by driving current generated by seventh transistor Tdr1 based on gate-source and drain-source voltage, as well as based on cut-off signal controlled via data voltage PWDA and sweep signal SWL)
wherein the first transistor, the second transistor, the third transistor, the seventh transistor, and the ninth transistor comprise N-type transistors (paragraph 131, all transistors of pixel circuit may be configured as N-type transistors).
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Regarding claim 2, Zhong discloses the pixel circuit of claim 1, further comprising a sixth transistor (fig. 10, transistor Ti2) comprising a control electrode configured to receive a first initialization signal (fig. 10, signal SL4), a first electrode connected to the first node (fig. 10, node N4), and a second electrode connected to a first initialization voltage terminal and to a second electrode of the ninth transistor (paragraph 125, 133, see annotated figure below).
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Regarding claim 3, Zhong discloses the pixel circuit of claim 1, further comprising a first capacitor (fig. 10, capacitor C2) comprising a first electrode configured to receive a sweep signal (fig. 10, signal SWL), and a second electrode connected to the first node (fig. 10, node N4, paragraph 117, see annotate figure below).
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Regarding claim 4, Zhong discloses the pixel circuit of claim 1, further comprising:
a fourth transistor (fig. 10, transistor Ts3) comprising a control electrode configured to receive a first emission signal (fig. 10, branch of EML signal connected to Ts3 control electrode), a first electrode configured to receive the first power voltage (fig. 10, voltage Vdd_PWM), and a second electrode connected to the second node (fig. 10, node above N6); and
a fifth transistor (fig. 10, transistor Ts4) comprising a control electrode configured to receive a second emission signal (fig. 10, branch of EML signal connected to Ts4 control electrode), a first electrode connected to the third node (fig. 3, node N5), and a second electrode connected to the fourth node (fig. 3, node N1, see annotated figure below).
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Regarding claim 5, Zhong discloses the pixel circuit of claim 1, further comprising an eighth transistor (fig. 10, transistor Ts2) comprising a control electrode configured to receive a first emission signal (fig. 10, signal EML), a first electrode connected to a second electrode of the seventh transistor (fig. 10, node N3), and a second electrode connected to an anode electrode of the light-emitting element (fig. 10, Ts2 connected to anode of LED Di, see annotated figure below).
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Regarding claim 6, Zhong discloses the pixel circuit of claim 1, further comprising an eighth transistor (fig. 10, transistor Ts1) comprising a control electrode configured to receive a first emission signal (fig. 10, signal EML), a first electrode configured to receive a second power voltage (fig. 10, voltage Vdd_PAM), and a second electrode connected to a first electrode of the seventh transistor (fig. 10, transistor Tdr1, see annotated figure below).
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Regarding claim 7, Zhong discloses the pixel circuit of claim 1, further comprising a tenth transistor (fig. 10, transistor Ti3) comprising a control electrode configured to receive a second initialization signal (fig. 10, signal DisL), a first electrode connected to an anode electrode of the light-emitting element (fig. 10, anode of LED Di), and a second electrode configured to receive a second initialization voltage (fig. 10, signal VL2, see annotated figure below).
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Regarding claim 9, Zhong discloses the pixel circuit of claim 1, wherein, in a light-emission period, the first transistor is configured to be turned off, the seventh transistor is configured to be turned on, and the light-emitting element is configured to emit a light, and wherein, in a light-mission-off period, the first transistor is configured to be turned on, the seventh transistor is configured to be turned off, and the light-emitting element is configured to stop emitting light (paragraphs 139-140, the turning on/off of seventh transistor Tdr1 to control light emission of LED Di is controlled via turning off/on of first transistor Tdr2 respectively, “light emitting phase t3…a driving current flows through the light emitting device Di to start light emission of the light emitting device Di … the gate-source voltage difference of the second driving transistor Tdr2 is greater than or equal to the threshold voltage of the second driving transistor Tdr2 (i.e., vgs_tdr2 is greater than or equal to vth_tdr2), and the second driving transistor Tdr2 maintains an off state. The voltage of the Sweep signal Sweep received by the pixel driving circuit 10 starts to drop, the potential of the fourth node N4 is coupled through the second capacitor C2, when the voltage difference between the gate and the source of the second driving transistor Tdr2 is smaller than the threshold voltage of the second driving transistor Tdr2 (vgs_tdr2 < vth_tdr2), the second driving transistor Tdr2 is turned on, the high voltage supplied by the second power supply terminal vdd_pwm is transmitted to the first node N1 through the third switching transistor Ts3, the second driving transistor Tdr2 and the fourth switching transistor Ts4, so that the voltage difference between the gate and the source of the first driving transistor Tdr1 is larger than or equal to the threshold voltage of the first driving transistor Tdr1 (that is, vgs_tdr1 is larger than or equal to vth_tdr1), the first driving transistor Tdr1 is turned off, and the light emitting device Di stops emitting light).
Regarding claim 10, Zhong discloses the pixel circuit of claim 1, further comprising a fourth transistor (fig. 10, transistor Ts3) comprising a control electrode configured to receive a first emission signal (fig. 10, signal EML), a first electrode configured to receive the first power voltage (fig. 10, voltage Vdd_PWM), and a second electrode connected to the second node (fig. 10, node above N6),
wherein a second power voltage (fig. 10, voltage Vdd_PAM) is configured to be applied to a first electrode of the seventh transistor (fig. 10, transistor Tdr1), and
wherein the first power voltage is less than the second power voltage (paragraph 128, Vdd_PWM < Vdd_PAM, see annotated figure below).
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Regarding claim 12, Zhong discloses the pixel circuit of claim 1, wherein the second transistor (fig. 10, transistor Tc2) comprises a control electrode configured to receive a first scan signal (fig. 10, signal SL3), a first electrode connected to the first node (fig. 10, node N4), and a second electrode connected to the second node (fig. 10, node above N6),
wherein the third transistor (fig. 10, transistor Tda2) comprises a control electrode configured to receive the first scan signal (fig. 10, signal SL3), a first electrode configured to receive the data voltage (fig. 10, data voltage PWDA), and a second electrode connected to the third node (fig. 10, node N5),
wherein the seventh transistor (fig. 10, transistor, Tdr1) comprises a control electrode connected to the fourth node (fig. 10, node N1), a first electrode configured to receive a second power voltage (fig. 10, voltage Vdd_PAM), and a second electrode connected to a fifth node (fig. 10, anode of Di),
wherein the ninth transistor (fig. 10, transistor Ti1) comprises a control electrode configured to receive a second scan signal (fig. 10, signal SL2), a first electrode connected to the fourth node (fig. 10, node N1), and a second electrode connected to a first initialization voltage terminal (fig. 10, terminal VL1), and
wherein the light-emitting element comprises an anode electrode (fig. 10, anode of Di), and a cathode electrode configured to receive a third power voltage (fig. 10, cathode of Di connected to VSS, see annotated figure below).
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Regarding claim 19, Zhong discloses a display apparatus comprising:
a display panel comprising a pixel circuit (fig. 4A~4C, 7A, paragraphs 65-67, display panel comprising plurality of pixel circuit);
a gate driver configured to output a gate signal to the pixel circuit (paragraph 67, gate driving unit configured to output gate scanning signal Scan); and
a data driver configured to output a data voltage to the pixel circuit (fig. 4A-4C, paragraphs 27-33, 37-40, 54, display panel contain circuit configured to generate pulse width modulation control data voltage PWDA),
wherein the pixel circuit comprises:
a first transistor (fig. 10, transistor Tdr2) comprising a control electrode connected to a first node (fig. 10, node N4), a first electrode connected to, and configured to receive a first power voltage (fig. 10, voltage Vdd_PWM) from, a second node (fig. 10, see annotated second node and first electrode below), and a second electrode connected to a third node (fig. 10, node N5);
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a second transistor (fig. 10, transistor Tc2) connected to the first node (fig. 10 node N4) and the second node (fig. 10, node above N6);
a third transistor (fig. 10, transistor Tda2) configured to apply a data voltage (fig. 10, PWDA) to the first transistor;
a seventh transistor (fig. 10, transistor Tdr1) connected to a fourth node (fig. 10, node N1), and configured to apply a driving current to a light-emitting element (fig. 10, light-emitting element Di) ;
a ninth transistor (fig. 10, transistor Ti1) configured to apply a constant-current voltage (fig. 10, VL1) to the fourth node (fig. 10, node N1); and
the light-emitting element configured to emit a light based on the data voltage and the constant-current voltage (see details of pixel circuit operation in paragraph 100-141, in particular, light emitting diode Di emit light controlled by driving current generated by seventh transistor Tdr1 based on gate-source and drain-source voltage, as well as based on cut-off signal controlled via data voltage PWDA and sweep signal SWL)
wherein the first transistor, the second transistor, the third transistor, the seventh transistor, and the ninth transistor comprise N-type transistors (paragraph 131, all transistors of pixel circuit may be configured as N-type transistors).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zhong, as applied in claim 1 above, and in further view of Zhang, CN 117475817 A (hereinafter “Zhang”).
Regarding claim 8, Zhong discloses the pixel circuit of claim 1.
Zhong does not disclose in particular:
a second capacitor comprising a first electrode connected to the fourth node, and a second electrode connected to a second electrode of the seventh transistor; and
a third capacitor comprising a first electrode configured to receive a second power voltage, and a second electrode connected to the fourth node.
In similar field of endeavor of pixel driving circuit with pulse width modulation control of light emitting device, Zhang discloses similar pixel circuit (paragraphs 25, 26) with a driving transistor configured to apply a driving current to a light-emitting element (fig. 6, paragraphs 29-33, transistor T1 controlling light-emitting element D, corresponding to “seventh transistor” of instant application, transistor T1 connected to a fourth node G) and controlling transistor controlling pulse width (fig. 6, paragraphs 29-33 transistor T7, corresponding to “first transistor” of instant application), with
a second capacitor comprising a first electrode connected to the fourth node, and a second electrode connected to a second electrode of the seventh transistor; and a third capacitor comprising a first electrode configured to receive a second power voltage, and a second electrode connected to the fourth node (fig. 2, paragraph 34, see annotated figure below).
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It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of capacitors between gate/source of driving transistor, as well as capacitor between voltage supply and gate of driving transistor, such as disclosed by Zhang, into the pixel circuit of Zhong, to constitute a second capacitor comprising a first electrode connected to the fourth node, and a second electrode connected to a second electrode of the seventh transistor; and a third capacitor comprising a first electrode configured to receive a second power voltage, and a second electrode connected to the fourth node, such is incorporation of a known technique into a known device to yield predictable result, the result would have been predictable and would allow capacitor to maintain and hold driving voltage between gate-source and drain-source of driving transistor of pixel circuit to improve stability of pixel driving.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zhong, as applied in claim 1 above, and in further view of Chen et al., US 20200126483 A1 (hereinafter “Chen”).
Regarding claim 11, Zhong discloses the pixel circuit of claim 1, further comprising a tenth transistor (fig. 10, transistor DisL) comprising a control electrode configured to receive a second initialization signal (fig. 10, signal DisL), a first electrode connected to an anode electrode of the light-emitting element (fig. 10, LED Di), and a second electrode configured to receive a second initialization voltage (fig. 10, voltage VL2),
wherein a third power voltage is configured to be applied to a cathode electrode of the light-emitting element (fig. 10, power VSS applied to LED Di, see annotated figure below).
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Zhong only does not specifically disclose wherein the second initialization voltage is less than the third power voltage.
In similar field of endeavor of initializing anode electrode of light emitting element in display, Chen discloses that second initialization applied to anode of light emitting element is less than a third power voltage applied to cathode of light emitting element (fig. 3, initialization voltage Vref applied to anode of light emitting element 310 and third power voltage ELVSS applied to cathode of light emitting element, paragraph 38, Vref is less than the third power voltage, paragraph 38, “…during the recovery period, the voltage supply circuit 120 supplies a reverse bias voltage (which is higher than the common voltage) to the common voltage line ELVSS of the display panel 110 and supplies a low voltage (e.g., a negative voltage or any other voltage lower than the reverse bias voltage) to the initializing voltage line VREF, so as to reversely bias the OLED 310…When the sixth switch 346 is turned on, the OLED 310 may be reversely biased by the low voltage of the initializing voltage line VREF and the reverse bias voltage (i.e., the high voltage) of the common voltage line ELVSS. After the OLED 310 has been reversely biased for a period of time, photoelectric characteristics of the OLED 310 may be considerably recovered).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of configuring anode initialization voltage to be less than cathode supply voltage of light emitting element in pixel circuit, such as disclosed by Chen, into the device of Zhong, to constitute wherein the second initialization voltage is less than the third power voltage, such is incorporation of a known technique into a known device to yield predictable result, the result would have been predictable and would allow photoelectric characteristic of light emitting element in pixel circuit to reset during initialization stage.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Zhong, as applied in claim 1 above, and in further view of Rho et al., US 20070024557 A1 (hereinafter “Rho”).
Regarding claim 20, Zhong discloses an electronic apparatus comprising:
a display panel comprising a pixel circuit (fig. 4A~4C, 7A, paragraphs 65-67, display panel comprising plurality of pixel circuit);
a gate driver configured to output a gate signal to the pixel circuit (paragraph 67, gate driving unit configured to output gate scanning signal Scan); and
a data driver configured to output a data voltage to the pixel circuit (fig. 4A-4C, paragraphs 27-33, 37-40, 54, display panel contain circuit configured to generate pulse width modulation control data voltage PWDA),
wherein the pixel circuit comprises:
a first transistor (fig. 10, transistor Tdr2) comprising a control electrode connected to a first node (fig. 10, node N4), a first electrode connected to, and configured to receive a first power voltage (fig. 10, voltage Vdd_PWM) from, a second node (fig. 10, see annotated second node and first electrode below), and a second electrode connected to a third node (fig. 10, node N5);
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a second transistor (fig. 10, transistor Tc2) connected to the first node (fig. 10 node N4) and the second node (fig. 10, node above N6);
a third transistor (fig. 10, transistor Tda2) configured to apply a data voltage (fig. 10, PWDA) to the first transistor;
a seventh transistor (fig. 10, transistor Tdr1) connected to a fourth node (fig. 10, node N1), and configured to apply a driving current to a light-emitting element (fig. 10, light-emitting element Di) ;
a ninth transistor (fig. 10, transistor Ti1) configured to apply a constant-current voltage (fig. 10, VL1) to the fourth node (fig. 10, node N1); and
the light-emitting element configured to emit a light based on the data voltage and the constant-current voltage (see details of pixel circuit operation in paragraph 100-141, in particular, light emitting diode Di emit light controlled by driving current generated by seventh transistor Tdr1 based on gate-source and drain-source voltage, as well as based on cut-off signal controlled via data voltage PWDA and sweep signal SWL)
wherein the first transistor, the second transistor, the third transistor, the seventh transistor, and the ninth transistor comprise N-type transistors (paragraph 131, all transistors of pixel circuit may be configured as N-type transistors).
Zhong only does not specifically outline the electronic device further comprises a driving controller configured to control the gate driver and the data driver; and a processor configured to output input image data and an input control signal to the driving controller.
The concept of display device with processor to process image signal and driving controller to control gate driver and data driver, however, is widely known in the field of art, such as disclosed by Rho, which discloses a display device with a driving controller configured to control the gate driver and the data driver; and a processor configured to output input image data and an input control signal to the driving controller of display device (fig. 1-3, paragraphs 31, 32, display device with processor 100 and driving controller 280).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of processor and driving controller to control display device, such as disclosed by Rho, into the device of Zhong, to constitute a driving controller configured to control the gate driver and the data driver; and a processor configured to output input image data and an input control signal to the driving controller, such is incorporation of a known technique into a known device to yield predictable result, the result would have been predictable and would allow display device to control and supply image signal to pixel circuit to display image.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3, 4, 7, 11, 12, 13 and 14 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 5, 8, 12, 15 and 16 of copending Application No. 19079304 (reference application), in view of Zhong, CN 112927651 B (hereinafter “Zhong”).
The following is comparison of claims of instant application and reference application:
Pending application
Claims of 19079304
1. A pixel circuit comprising:
a first transistor including a control electrode connected to a first node, a first electrode connected to and configured to receive a first power voltage from, a second node and a second electrode connected to a third node;
a second transistor connected to the first node and the second node;
a third transistor configured to apply a data voltage to the first transistor;
a seventh transistor connected to a fourth node and configured to apply a driving current to a light emitting element;
a ninth transistor configured to apply a constant-current voltage to the fourth node; and
the light emitting element configured to emit a light based on the data voltage and the constant-current voltage,
wherein the first transistor is an N-type transistor, and
wherein the seventh transistor is a P-type transistor.
1. A pixel circuit comprising:
a first transistor including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node;
a second transistor connected to the first node and the second node;
a third transistor configured to apply a data voltage to the first transistor;
a seventh transistor connected to a fourth node and configured to apply a driving current to a light emitting element;
a ninth transistor configured to apply a constant-current voltage to the fourth node; and
the light emitting element configured to emit a light based on the data voltage and the constant-current voltage,
wherein the first transistor is an N-type transistor, and
wherein the seventh transistor is a P-type transistor.
3. The pixel circuit of claim 1, further comprising a first capacitor comprising a first electrode configured to receive a sweep signal, and a second electrode connected to the first node.
4. The pixel circuit of claim 1, further comprising a first capacitor including a first electrode configured to receive a sweep signal and a second electrode connected to the first node.
4. The pixel circuit of claim 1, further comprising:
a fourth transistor comprising a control electrode configured to receive a first emission signal, a first electrode configured to receive a first power voltage, and a second electrode connected to the second node; and
a fifth transistor comprising a control electrode configured to receive a second emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node.
5. The pixel circuit of claim 1, further comprising:
a fourth transistor including a control electrode configured to receive a first emission signal, a first electrode configured to receive a first power voltage and a second electrode connected to the second node; and
a fifth transistor including a control electrode configured to receive a second emission signal, a first electrode connected to the third node and a second electrode connected to the fourth node.
7. The pixel circuit of claim 1, further comprising a tenth transistor comprising a control electrode configured to receive a second initialization signal, a first electrode connected to an anode electrode of the light-emitting element, and a second electrode configured to receive a second initialization voltage.
8. The pixel circuit of claim 1, further comprising a tenth transistor including a control electrode configured to receive a second initialization signal, a first electrode connected to an anode electrode of the light emitting element and a second electrode configured to receive a second initialization voltage.
11. The pixel circuit of claim 1, further comprising
a tenth transistor comprising a control electrode configured to receive a second initialization signal,
a first electrode connected to an anode electrode of the light-emitting element, and a second electrode configured to receive a second initialization voltage,
wherein a third power voltage is configured to be applied to a cathode electrode of the light-emitting element, and
wherein the second initialization voltage is less than the third power voltage.
12. The pixel circuit of claim 1, further comprising
a tenth transistor including a control electrode configured to receive a second initialization signal,
a first electrode connected to an anode electrode of the light emitting element and a second electrode configured to receive a second initialization voltage,
wherein a third power voltage is applied to a cathode electrode of the light emitting element, and
wherein the second initialization voltage is less than the third power voltage.
12. The pixel circuit of claim 1,
wherein the second transistor comprises a control electrode configured to receive a first scan signal, a first electrode connected to the first node, and a second electrode connected to the second node,
wherein the third transistor comprises a control electrode configured to receive the first scan signal, a first electrode configured to receive the data voltage, and a second electrode connected to the third node,
wherein the seventh transistor comprises a control electrode connected to the fourth node, a first electrode configured to receive a second power voltage, and a second electrode connected to a fifth node,
wherein the ninth transistor comprises a control electrode configured to receive a second scan signal, a first electrode connected to the fourth node, and a second electrode connected to a first initialization voltage terminal, and
wherein the light-emitting element comprises an anode electrode, and a cathode electrode configured to receive a third power voltage.
15. The pixel circuit of claim 1,
wherein the second transistor includes a control electrode configured to receive a first scan signal, a first electrode connected to the first node and a second electrode connected to the second node,
wherein the third transistor includes a control electrode configured to receive the first scan signal, a first electrode configured to receive the data voltage and a second electrode connected to the third node,
wherein the seventh transistor includes a control electrode connected to the fourth node, a first electrode connected to a fifth node and a second electrode connected to an anode electrode of the light emitting element,
wherein the ninth transistor includes a control electrode configured to receive a second scan signal, a first electrode connected to the fourth node and a second electrode connected to a first initialization voltage terminal, and
wherein the light emitting element includes the anode electrode and a cathode electrode configured to receive a third power voltage.
13. The pixel circuit of claim 12, further comprising:
a fourth transistor comprising a control electrode configured to receive a first emission signal, a first electrode configured to receive a first power voltage, and a second electrode connected to the second node;
a fifth transistor comprising a control electrode configured to receive a second emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node;
a sixth transistor comprising a control electrode configured to receive a first initialization signal, a first electrode connected to the first node, and a second electrode connected to the first initialization voltage terminal;
an eighth transistor comprising a control electrode configured to receive the first emission signal, a first electrode connected to the fifth node, and a second electrode connected to the anode electrode of the light-emitting element;
a tenth transistor comprising a control electrode configured to receive a second initialization signal, a first electrode connected to the anode electrode of the light-emitting element, and a second electrode configured to receive a second initialization voltage;
a first capacitor comprising a first electrode configured to receive a sweep signal, and a second electrode connected to the first node; and
a second capacitor comprising a first electrode connected to the fourth node, and a second electrode connected to the fifth node.
16. The pixel circuit of claim 15, further comprising:
a fourth transistor including a control electrode configured to receive a first emission signal, a first electrode configured to receive a first power voltage and a second electrode connected to the second node;
a fifth transistor including a control electrode configured to receive a second emission signal, a first electrode connected to the third node and a second electrode connected to the fourth node;
a sixth transistor including a control electrode configured to receive a first initialization signal, a first electrode connected to the first node and a second electrode connected to the first initialization voltage terminal;
an eighth transistor including a control electrode configured to receive the first emission signal, a first electrode configured to receive a second power voltage and a second electrode connected to the fifth node;
a tenth transistor including a control electrode configured to receive a second initialization signal, a first electrode connected to the anode electrode of the light emitting element and a second electrode configured to receive a second initialization voltage;
a first capacitor including a first electrode configured to receive a sweep signal and a second electrode connected to the first node; and
a second capacitor including a first electrode configured to receive the second power voltage and a second electrode connected to the fourth node.
14. The pixel circuit of claim 13, wherein the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor, and the tenth transistor comprise N-type transistors.
17. The pixel circuit of claim 16, wherein the second transistor, the third transistor, the sixth transistor and the ninth transistor are N-type transistors, and
Reviewing claims of pending application and reference application, the difference between pending claims and reference claims is that reference application specifies the seventh transistor to be a P-type transistor instead of a N-type transistor, and reference application does not specify that the fourth, fifth, eighth and tenth transistor are N-type transistor. In addition, the reference application does not specifically claim the first electrode of the first transistor is connected to, and configured to receive a first power voltage from the second node.
In similar filed of endeavor, Zhong discloses a pixel circuit (fig. 10) comprising:
a first transistor (fig. 10, transistor Tdr2) comprising a control electrode connected to a first node (fig. 10, node N4), a first electrode connected to, and configured to receive a first power voltage (fig. 10, voltage Vdd_PWM) from, a second node (fig. 10, see annotated second node and first electrode below), and a second electrode connected to a third node (fig. 10, node N5);
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a second transistor (fig. 10, transistor Tc2) connected to the first node (fig. 10 node N4) and the second node (fig. 10, node N6);
a third transistor (fig. 10, transistor Tda2) configured to apply a data voltage (fig. 10, PWDA) to the first transistor;
a seventh transistor (fig. 10, transistor Tdr1) connected to a fourth node (fig. 10, node N1), and configured to apply a driving current to a light-emitting element (fig. 10, light-emitting element Di) ;
a ninth transistor (fig. 10, transistor Ti1) configured to apply a constant-current voltage (fig. 10, VL1) to the fourth node (fig. 10, node N1); and
the light-emitting element configured to emit a light based on the data voltage and the constant-current voltage (see details of pixel circuit operation in paragraph 100-141, in particular, light emitting diode Di emit light controlled by driving current generated by seventh transistor Tdr1 based on gate-source and drain-source voltage, as well as based on cut-off signal controlled via data voltage PWDA and sweep signal SWL)
wherein the first transistor, the second transistor, the third transistor, the seventh transistor, and the ninth transistor comprise N-type transistors (paragraph 131, all transistors of pixel circuit may be configured as N-type transistors).
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Zhong further discloses a fourth, fifth, sixth, eighth, and tenth transistors corresponding to fourth, fifth, sixth, eighth, and tenth transistor of reference application, all of which may be configured as N-type transistor (see annotated figure below), and that all transistors may be configured as N-type transistor.
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It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of configuring driving transistors of pixel circuit to be N-type transistor, and having first electrode of the first transistor receive first power from the second node, such as disclosed by Zhong, into reference application, to constitute wherein the fourth, fifth, seventh, eighth and tenth transistor are N-type transistor, and the first electrode of the first transistor is connected to, and configured to receive a first power voltage from the second node. Such is incorporation of known technique into known device yield predictable result, the result would have been predictable and would allow the display device to drive pixel circuit with the same function of PWM light emission control to display intended image.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEIJIE SHEN whose telephone number is (571)272-5522. The examiner can normally be reached Monday - Friday 10AM - 6PM.
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/PEIJIE SHEN/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
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