Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed February 10, 2025.
Status of claims to be treated in this office action:
a. Independent: 1, 11
b. Pending: 1-20
Specification
The disclosure is objected to because of the following informalities:
Regarding para. [0034] of the Detailed Description section, make the following change:
“[[For]]Although the embodiment below is described in detail with the accompanying drawings, embodiments are not provided to limit the scope of the present disclosure.”
Regarding para. [0038] of the Detailed Description section, make the following changes:
“In one embodiment, the processing circuit 120 can include a control circuit 121 and an encoding circuit 122, the control circuit 121 is configured to provide an original data [[of]]for the vector-matrix multiplication, and the encoding circuit 122 is configured to encode the original data [[to]]as input [[to]]for the memory array 110.”
Regarding para. [0039] of the Detailed Description section, make the following change:
“When performing the vector-matrix multiplication, the processing circuit 120 is configured to provide the input data [[of]]for the vector-matrix multiplication”
Regarding para. [0040] of the Detailed Description section, make the following changes:
“The sensing circuit 130 is coupled to the memory array 110, and is configured to receive the output signal from the memory array 110. In one embodiment, the sensing circuit 130 receives multiple output currents of the memory strings MR, and calculates a current sum value of all output currents to generate the output signal. In one embodiment, the sensing circuit 130 also calculates [[a]]an impedance sum value according to the current sum value as the output signal (i.e., calculation result).”
Regarding para. [0041] of the Detailed Description section, make the following change:
“FIG. 2 is a schematic diagram of multiple memory strings in some embodiments of the present disclosure. The memory strings MR1-MRN can be implemented [[to]]in any one of the memory blocks BLK shown in FIG. 1.”
Regarding para. [0043] of the Detailed Description section, make the following changes:
“Each of the memory strings MR1-MRN generates a unit current according to the preset weight values and the received read voltage, and all unit currents are [[outputs]]outputted to the sensing circuit 130 through a common source line CSL to calculate the result. In one embodiment, the processing circuit 120 can generate an operation code (e.g., binary code) according to each operation data, and uses the operation codes as a digital voltage signal[[,]]. [[the]]The details will be detailed in the subsequent paragraphs.”
Examiner notes that “outputs” could be changed to either “output” or “outputted”.
Regarding para. [0043] of the Detailed Description section, make the following changes:
“In some embodiments, thestrings can be used as a multiple calculation weight unit 210, and are configured to be set the calculation weight values. Each memory string further includes at least one balanced weight unit 220 and at least one series weight unit 230. The balanced weight unit 220 is configured to adjust the equivalent impedance value of each memory string, and is configured to [[be]] adjust the standard deviation of all weight values.”
Appropriate correction is required.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Memory device and memory operation method with processing circuit to perform vector-matrix multiplication.
Claim Objections
Claim 6 is objected to because of the following informality:
Regarding claim 6, on p.2, on the second line of the claim, make the following change:
“the first partition accounts
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US Pub. 20220075600 A1; “Hu”) in view of Mohajer et al. (US Pub. 20190121839 A1; “Mohajer”) and Wang et al. (US Pub. 20260105966 A1; “Wang”).
Regarding independent claim 1, Hu discloses a memory operation method ([0010]: provided is an operation method for a memory device. The operation method includes: storing a plurality of weights in a plurality of memory cells of a memory array of the memory device; performing bitwise multiplication…), comprising:
obtaining an operation code of a vector-matrix multiplication ([0045]: The multiplication operation is performed on the input data (represented in the unFDP format) and the weights to generate an MAC operation result), the memory array comprises a plurality of memory strings ([0099]: One embodiment of the application is applied to NAND type flash memory. Examiner concludes that the array comprises strings because NAND flash memory typically has strings), and the operation code comprises a plurality of operation bits ([0037]: the input data (or the weight) is represented by a binary 8-bit format);
converting a first partition of the plurality of operation bits into a first conversion code, wherein a format of the first conversion code is different from a format of the operation code ([0037]: When the input data (or the weight) is represented by a binary 8-bit format, the input data (or the weight) includes a most significant bit (MSB) vector and a least significant bit (LSB) vector. The MSB vector of the 8-bit input data (or the weight) includes bits B7 to B4 and the LSB vector of the 8-bit input data (or the weight) includes bits B3 to B0; [0038]: Each bit of the MSB vector and the LSB vector of the input data is represented into unary code (value format). Examiner asserts that the “MSB vector” is analogous to a “first partition” and the MSB vector is converted from binary to unary); and
Hu does not disclose:
obtaining, by a processing circuit, an operation code
wherein the processing circuit is coupled to a memory array,
using the first conversion code and a second partition of the plurality of operation bits as an input data, and inputting the input data to a corresponding one of the plurality of memory strings, so that the plurality of memory strings generates an output signal according to a plurality of weight values.
However, Mohajer teaches:
obtaining, by a processing circuit, an operation code ([0042]: techniques are described herein by which bit stream 114 is processed by stochastic logic circuitry 120 so that each of the computational units within the stochastic logic circuitry may nevertheless apply stochastic operations on the bit streams; [0137]: The term “processor” or “processing circuitry” may generally refer to any of the foregoing logic circuitry, alone or in combination with other logic circuitry, or any other equivalent circuitry. Examiner concludes that the stochastic logic circuitry is analogous to a processing circuit)
wherein the processing circuit is coupled to a memory array ([0139]: Instructions embedded or encoded in…a non-transitory computer-readable storage medium encoded, may cause one or more programmable processors, or other processors, to implement one or more of the techniques described herein, such as when instructions included or encoded in the non-transitory computer-readable storage medium are executed by the one or more processors. Example non-transitory computer-readable storage media may include RAM…flash memory),
using the first conversion code and a second partition of the plurality of operation bits as an input data (claim 5: convert a first portion of an input binary number to the input unary bit stream…produce at least two output unary bit streams… convert the at least two output unary bit streams to at least two output binary numbers; and a first multiplexer configured to select one output binary number of the at least two output binary numbers based on a second portion of the input binary number; also see Fig. 12, in which the lower M bits are converted to unary format while the upper N-M bits are not. Examiner asserts that the “input unary bit stream” is analogous to a first conversion code and the “second portion” is analogous to a second partition), and
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Mohajer to
Hu wherein the method comprises obtaining, by a processing circuit, an operation code wherein the processing circuit is coupled to a memory array, using the first conversion code and a second partition of the plurality of operation bits as an input data in order to implement methods to perform parallel computation using stochastic logic operations (Mohajer, [0031]).
Also, through Wang:
inputting the input data to a corresponding one of the plurality of memory strings, so that the plurality of memory strings generates an output signal according to a plurality of weight values ([0108]: The current from any given NAND string is the product of the weight stored in the selected memory cell in the NAND string and the magnitude at the relevant position of the input vector. Also refer to Fig. 16).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Wang to
modified Hu wherein inputting the input data to a corresponding one of the plurality of memory strings, so that the plurality of memory strings generates an output signal according to a plurality of weight values in order to implement an inference engine that performs vector-matrix multiplication with a pre-trained weight-based model (Wang, [0032]).
Regarding claim 2, Hu, Mohajer, and Wang together disclose the limitations of
claim 1. Further, through Hu:
wherein the first partition comprises a most significant bit of the plurality of operation bits ([0101]: the input data and/or the weight are divided into the MSB vector and the LSB vector (i.e. two vectors); [0037]).
Regarding claim 3, Hu, Mohajer, and Wang together disclose the limitations of
claim 2. Further, through Hu:
wherein the first partition of the plurality of operation bits has higher-order bits compared to the second partition (Fig. 2 and [0037] show that the MSB vector contains higher-order bits as compared to the LSB vector).
Regarding claim 4, Hu, Mohajer, and Wang together disclose the limitations of
claim 1. Further, through Hu:
wherein a number of bits in the first partition accounts for 40% to 60% of the plurality of operation bits ([0037]: The MSB vector of the 8-bit input data (or the weight) includes bits B7 to B4 and the LSB vector of the 8-bit input data (or the weight) includes bits B3 to B0. Examiner concludes that the MSB vector, analogous to the first partition, contains 50% of the plurality of operation bits).
Regarding claim 5, Hu, Mohajer, and Wang together disclose the limitations of
claim 1. Further, through Mohajer:
wherein a number of bits in the first partition is larger than a number of bits in the second partition ([0135]: Multiplexer 1250 can receive the upper N-M bits of the binary number…The upper M bits may be any number of bits, including one, two, three, or more bits; [0132]: The lower M bits may be any number of bits, including one, two, three, or more bits. Examiner notes that “upper M bits” in [0135] is a typo and should say “upper N-M bits” per Fig. 22. Per the above paras., as an example, the upper N-M bits may be two and the lower M bits may be one).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Mohajer to modified Hu wherein a number of bits in the first partition is larger than a number of bits in the second partition in order to implement methods to perform parallel computation using stochastic logic operations (Mohajer, [0031]).
Regarding claim 6, Hu, Mohajer, and Wang together disclose the limitations of
claim 5. Further, through Mohajer:
wherein a number of bits in the first partition accounts accounts for 70% to 95% of the plurality of operation bits (per rejection of claim 5 above, the upper N-M bits may be three bits and the lower M bits may be 1 bit. In that case, the upper N-M bits would account for 75% of the bits).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Mohajer to modified Hu wherein a number of bits in the first partition accounts for 70% to 95% of the plurality of operation bits in order to implement methods to perform parallel computation using stochastic logic operations (Mohajer, [0031]).
Regarding claim 8, Hu, Mohajer, and Wang together disclose the limitations of
claim 1. Further, through Hu:
wherein the format of the first conversion code is in unary encoding format ([0037]-[0038]).
Regarding claim 9, Hu, Mohajer, and Wang together disclose the limitations of
claim 1. Further, through Hu:
wherein the format of the operation code is in binary encoding format ([0037]).
Regarding claim 10, Hu, Mohajer, and Wang together disclose the limitations of
claim 1. Further, through Wang:
receiving a plurality of output currents of the plurality of memory strings; and
calculating a current sum value of the plurality of output currents to obtain the output signal ([0108]: The sensed output vector is a set of output currents sensed on bit lines 610. In one embodiment, each bit line is connected to one NAND string in every region of every block of a plane; therefore, the bit line can potentially receive current concurrently from multiple NAND strings (ie one NAND string in each region of each block of a plane). The current received at the bit line from the multiple NAND strings is added together such that the sense amplifier senses the sum of the current from the multiple NAND strings).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Wang to
modified Hu wherein the method comprises receiving a plurality of output currents of the plurality of memory strings; and calculating a current sum value of the plurality of output currents to obtain the output signal in order to implement an inference engine that performs vector-matrix multiplication with a pre-trained weight-based model (Wang, [0032]).
Independent claim 11 contains limitations that are mostly the same as the limitations of claim 1 except for being written in device format, and those limitations are thus rejected for the same reasons.
Further through Wang:
a memory array coupled to a plurality of word lines and a plurality of bit lines, and comprising a plurality of memory strings ([0077]: FIG. 4 is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array/structure that can comprise memory structure 202, which includes a plurality non-volatile memory cells arranged as vertical NAND strings…The structure depicted includes a set of bit lines BL positioned above a stack 401 of alternating dielectric layers and conductive layers…one of the conductive layers (also called word line layers) is marked as W);
a sensing circuit coupled to the memory array to obtain an output signal from the memory array ([0108]: senses an output vector from the bit lines 610 using the senses amplifiers (S/A) 230…The sensed output vector is a set of output currents sensed on bit lines 610. In one embodiment, each bit line is connected to one NAND string in every region of every block of a plane); and
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Wang to
modified Hu wherein the memory device comprises a memory array coupled to a plurality of word lines and a plurality of bit lines, and comprising a plurality of memory strings; and a sensing circuit coupled to the memory array to obtain an output signal from the memory array in order to implement an inference engine that performs vector-matrix multiplication with a pre-trained weight-based model (Wang, [0032]).
Regarding claim 12, Hu, Mohajer, and Wang discloses the limitations of claim 11. Claim 12 recites exactly the same as limitations as claim 2, and are thus rejected for the same reasons.
Regarding claim 13, Hu, Mohajer, and Wang discloses the limitations of claim 12. Claim 13 recites exactly the same as limitations as claim 3, and are thus rejected for the same reasons.
Regarding claim 14, Hu, Mohajer, and Wang discloses the limitations of claim 11. Claim 14 recites exactly the same as limitations as claim 4, and are thus rejected for the same reasons.
Regarding claim 15, Hu, Mohajer, and Wang discloses the limitations of claim 11. Claim 15 recites exactly the same as limitations as claim 5, and are thus rejected for the same reasons.
Regarding claim 16, Hu, Mohajer, and Wang discloses the limitations of claim 15. Claim 16 recites mostly the same as limitations as claim 6, and are thus rejected for the same reasons.
Regarding claim 18, Hu, Mohajer, and Wang discloses the limitations of claim 11. Claim 18 recites exactly the same as limitations as claim 8, and are thus rejected for the same reasons.
Regarding claim 19, Hu, Mohajer, and Wang discloses the limitations of claim 11. Claim 19 recites exactly the same as limitations as claim 9, and are thus rejected for the same reasons.
Regarding claim 20, Hu, Mohajer, and Wang discloses the limitations of claim 11. Claim 20 recites exactly the same as limitations as claim 10, and are thus rejected for the same reasons.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US Pub. 20220075600 A1), Mohajer (US Pub. 20190121839 A1) and Wang (US Pub. 20260105966 A1) as applied to claim 5 above, and further in view of Hu et al. (TW I783573 B; “Hu-TW”).
Regarding claim 7, Hu, Mohajer, and Wang together disclose the limitations of claim 5, and further through Mohajer:
wherein using the first conversion code and the second partition of the plurality of operation bits as the input data comprises (claim 5, Fig. 12):
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Mohajer to modified Hu wherein the method comprises using the first conversion code and the second partition of the plurality of operation bits as the input data in order to implement methods to perform parallel computation using stochastic logic operations (Mohajer, [0031]).
Neither Hu, Mohajer, nor Wang discloses:
converting the second partition of the plurality of operation bits into a second conversion code, wherein a format of the second conversion code is equal to the format of the first conversion code.
However, Hu-TW teaches:
converting the second partition of the plurality of operation bits into a second conversion code, wherein a format of the second conversion code is equal to the format of the first conversion code (p. 14, lines 9-13: The MSB and LSB of the input data are represented in binary form…each bit of the MSB and LSB of the weight value is represented in binary form…The MSB and LSB of the input data, as well as the MSB and LSB of the weight values, are encoded in unary code (numerical form)).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Hu-TW to modified Hu wherein the method comprises converting the second partition of the plurality of operation bits into a second conversion code, wherein a format of the second conversion code is equal to the format of the first conversion code in order to implement methods to perform parallel computation using stochastic logic operations (Mohajer, [0031]).
Regarding claim 17, Hu, Mohajer, and Wang discloses the limitations of claim 11. Claim 17 recites exactly the same as limitations as claim 7, and are thus rejected for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure:
Miao et al. (CN 114168107 B): paras. [n0010] and [n0040] are relevant to claims 1 and 11.
Zhang et al. (US Pub. 20220398438 A1): paras. [0026] and [0054], and Fig. 1 are relevant to claims 1 and 11.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rich Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/E.R.A./Examiner, Art Unit 2824
/SULTANA BEGUM/Primary Examiner, Art Unit 2824
9/1/2026
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