CTNF 19/049,097 CTNF 82556 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are pending in this office action and presented for examination. Specification 07-29 The disclosure is objected to because of the following informalities. Appropriate correction is required. In paragraph [0010], four instances of “circuity” should be “circuitry”. In paragraph [0080], line 3, there appear to be a space immediately preceding a period. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-01 Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites the limitation “a hazard circuit … configurable to: receive an indication from the memory of whether data associated with the load instruction will be returned within the latency of the memory” in lines 4-6. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [0073], [0077], [0080], [0082]) does not appear to provide support for a hazard circuit performing the aforementioned recited receiving. For example, the original disclosure (e.g., paragraph [0077]) does not appear to provide support for receiving an indication from the memory of whether data associated with the load instruction will be returned “within the latency of the memory”. Also see the limitation “the indication specifies that the data will not be returned within the latency of the memory” in claim 1, lines 12-13. Claim 1 recites the limitation “a hazard circuit … configurable to: determine whether to stall execution of the second instruction by the set of pipeline stages based on: whether the second instruction would attempt to utilize the data associated with the load instruction within the latency of the memory; and whether the second instruction would attempt to utilize the data associated with the load instruction and the indication specifies that the data will not be returned within the latency of the memory” in lines 4-13. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [0073], [0077], [0080], [0082]) does not appear to provide support for the hazard circuit performing the aforementioned determining. Claims 2-10 are rejected for failing to alleviate the rejections of claim 1 above. Claim 2 recites the limitation “the set of pipeline stages is configurable to provide a request for the data in response to the load instruction; and the request for the data includes a transaction identifier” in lines 1-5. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0078]) does not appear to provide support for the set of pipeline stages providing a transaction identifier in the request for the data. Claim 3 is rejected for failing to alleviate the rejection of claim 2 above. Claim 3 recites the limitation “the memory is configurable to provide the transaction identifier to the set of pipeline stages with the data” in lines 1-2. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0078]) does not appear to provide support for the memory providing the transaction identifier to the set of pipeline stages. Claim 4 recites the limitation “the set of pipeline stages is configurable to execute a third instruction while the second instruction is stalled” in lines 1-2. Claim 1, upon which claim 4 is dependent, recites the limitation “determine whether to stall execution of the second instruction by the set of pipeline stages based on: whether the second instruction would attempt to utilize the data associated with the load instruction within the latency of the memory; and whether the second instruction would attempt to utilize the data associated with the load instruction and the indication specifies that the data will not be returned within the latency of the memory” in lines 7-13. However, the original disclosure (e.g., paragraphs [0077]-[0078]) does not appear to provide support for executing a third instruction while the second instruction is stalled based on whether the second instruction would attempt to utilize the data associated with the load instruction within the latency of the memory; and whether the second instruction would attempt to utilize the data associated with the load instruction and the indication specifies that the data will not be returned within the latency of the memory. Claim 5 is rejected for failing to alleviate the rejection of claim 4 above. Claim 6 recites the limitation “the hazard circuit is configurable to: track a predetermined number of outstanding load instructions; and determine whether to stall the execution of the second instruction further based on whether the load instruction exceeds the predetermined number of outstanding load instructions” in lines 1-4. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [0073], [0077], [0080], [0082]) does not appear to provide support for the hazard circuit performing the aforementioned tracking and determining. Claim 8 recites the limitation “the hazard circuit is further configurable to: … based on the hazarding condition being resolved, restore the intermediate result of the third instruction to the set of pipeline stages from the second memory” in lines 5-10. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [0073], [0080], [0082], [0083]) does not appear to provide support for the hazard circuit performing the aforementioned restoring. Claims 9-10 are rejected for failing to alleviate the rejection of claim 8 above. Claim 10 recites the limitation “the hazard circuit is configurable to: maintain a lifetime tracking value for the third instruction; and determine where in the set of pipeline stages to restore the intermediate result of the third instruction based on the lifetime tracking value” in lines 1-4. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0076]) does not appear to provide support for the hazard circuit performing the aforementioned maintaining and determining. Claim 11 recites the limitation “a hazard circuit … configurable to: determine whether the second instruction utilizes a set of data returned by the load instruction” in lines 8-11. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [0073], [0077], [0080], [0082]) does not appear to provide support for the hazard circuit performing the aforementioned determining. For example, the original disclosure (e.g., paragraph [0077]) does not appear to provide support for determining whether the second instruction utilizes “a set of data” returned by the load instruction. Note that claim 12 recites the similar limitation “the second instruction would attempt to utilize the set of data of the load instruction” in lines 1-3. Claim 11 recites the limitation “a hazard circuit … configurable to: … receive, from the first memory, an indication of whether the set of data will be returned within the latency of the first memory” in lines 8-13. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [0073], [0077], [0080], [0082]) does not appear to provide support for the hazard circuit performing the aforementioned receiving. For example, the original disclosure (e.g., paragraph [0077]) does not appear to provide support for receiving, from the first memory, an indication of whether the set of data will be returned “within the latency of the first memory”. Also see the limitation “based on whether the set of data will be returned within the latency of the first memory” in claim 11, lines 19-20. For example, the original disclosure (e.g., paragraph [0077]) does not appear to provide support for receiving, from the first memory, an indication of whether “the set of data” will be returned within the latency of the first memory. Also see the limitation “the set of data will not be returned within the latency of the first memory” in claim 12, lines 3-4. Claim 11 recites the limitation “a hazard circuit … configurable to: … determine whether to stall execution of the second instruction based on whether the set of data will be returned within the latency of the first memory” in lines 8-15. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [0073], [0077], [0080], [0082]) does not appear to provide support for the hazard circuit performing the aforementioned determining. For example, the original disclosure (e.g., paragraph [0077]) does not appear to provide support for determining whether to stall execution of the second instruction based on whether the set of data will be returned “within the latency of the first memory”. For example, the original disclosure (e.g., paragraph [0077]) does not appear to provide support for determining whether to stall execution of the second instruction based on whether “the set of data” will be returned within the latency of the first memory. Also see the limitation “the set of data will not be returned within the latency of the first memory” in claim 12, lines 3-4. Claim 11 recites the limitation “a hazard circuit … configurable to: … determine whether the third instruction and the fourth instruction write to a same location within the first memory” in lines 8-17. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [0073], [0075], [0080], [0082]) does not appear to provide support for the hazard circuit performing the aforementioned determining. For example, the original disclosure (e.g., paragraph [0075]) does not appear to provide support for determining whether the third instruction and the fourth instruction write to a same location within the first memory. Also see the limitation “whether the third instruction and the fourth instruction write to a same location within the first memory” in claim 11, lines 19-20. Claim 11 recites the limitation “a hazard circuit … configurable to: … determine whether to store a result of the fourth instruction in the second memory until the third instruction completes based on whether the third instruction and the fourth instruction write to a same location within the first memory” in lines 8-20. For example, the original disclosure (e.g., paragraphs [0073], [0075], [0080], [0082]) does not appear to provide support for the hazard circuit performing the aforementioned determining whether to store a result. For example, the original disclosure (e.g., paragraph [0075]) does not appear to provide support for [determining] whether the third instruction and the fourth instruction write to a same location within the first memory. For example, the original disclosure (e.g., paragraph [0075], [0077], [0078]) does not appear to provide support for storing a result of the fourth instruction in the second memory until the third instruction completes based on whether the third instruction and the fourth instruction write to a same location within the first memory. Claims 12-14 are rejected for failing to alleviate the rejections of claim 11 above. Claim 12 recites the limitation “the hazard circuit is configurable to stall the second instruction based on either: the second instruction would attempt to utilize the set of data of the load instruction within the latency of the first memory or the set of data will not be returned within the latency of the first memory” in lines 1-4. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [0073], [0077], [0080], [0082]) does not appear to provide support for the hazard circuit performing the aforementioned stalling. Claim 13 recites the limitation “the hazard circuit is configurable to: track a predetermined number of outstanding load instructions; and stall the execution of the second instruction further when the load instruction exceeds the predetermined number of outstanding load instructions” in lines 1-4. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [0073], [0077], [0080], [0082]) does not appear to provide support for the hazard circuit performing the aforementioned tracking and stalling. Claim 14 recites the limitation “hazard circuit is configurable to, after completion of the third instruction, cause the result of the fourth instruction to be provided by the second memory and stored in the first memory” in lines 1-3. For example, the original disclosure (e.g., paragraphs [0073], [0075], [0080], [0082]) does not appear to provide support for the hazard circuit performing the aforementioned providing. For example, the original disclosure (e.g., paragraphs [0075], [0077]) does not appear to provide support for, after completion of the third instruction, causing the result of the fourth instruction to be provided by the second memory and stored in the first memory. Claim 15 recites the limitation “receiving, from a memory, an indication of whether a set of data will be received within a latency period of the memory” in lines 2-3. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0077]) does not appear to provide support for receiving, from a memory, an indication of whether a set of data will be received “within a latency period of the memory”. Also see the limitation “based on whether the set of data will be received within the latency period” in claim 15, lines 4-5. For example, the original disclosure (e.g., paragraph [0077]) does not appear to provide support for receiving, from a memory, an indication of whether “a set of data” will be received within a latency period of the memory. Claim 15 recites the limitation “determining whether to stall a second instruction that utilizes the set of data based on whether the set of data will be received within the latency period” in lines 2-3. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0077]) does not appear to provide support for determining whether to stall a second instruction that utilizes “the set of data” based on whether “the set of data” will be received within the latency period. Claims 16-20 are rejected for failing to alleviate the rejections of claim 15 above. Claim 16 recites the limitation “the determining of whether to stall the second instruction is further based on whether the second instruction would attempt to utilize the set of data during the latency period associated with the set of data” in lines 1-3. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0077]) does not appear to provide support for determining whether the second instruction would attempt to utilize “the set of data” during the latency period associated with “the set of data”. Claim 17 recites the limitation “providing, to the memory, a transaction identifier associated with the set of data; and receiving, from the memory, the transaction identifier in conjunction with the set of data” in lines 2-3. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0078]) does not appear to provide support for providing, to the memory, a transaction identifier associated with “the set of data”; and receiving, from the memory, the transaction identifier in conjunction with “the set of data”. Claim 18 recites the limitation “the method of claim 15 further comprising: stalling the second instruction; and executing a third instruction while the second instruction is stalled” in lines 1-3. Claim 15, upon which claim 18 is dependent, recites the limitation “receiving, from a memory, an indication of whether a set of data will be received within a latency period of the memory; and determining whether to stall a second instruction that utilizes the set of data based on whether the set of data will be received within the latency period” in lines 2-5. However, the original disclosure (e.g., paragraphs [0077]-[0078]) does not appear to provide support for executing a third instruction while the second instruction is stalled based on whether the set of data will be received within the latency period. Claim 19 recites the limitation “the determining of whether to stall the second instruction is further based on whether a load instruction associated with the set of data exceeds a predetermined number of outstanding load instructions” in lines 1-3. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0077]) does not appear to provide support for [determining] whether a load instruction associated with “the set of data” exceeds a predetermined number of outstanding load instructions. 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation “receive an indication from the memory of whether data associated with the load instruction will be returned within the latency of the memory” in lines 5-6. However, it is indefinite as to how data can be returned within a latency of the memory. Note that claim 1 further recites “the indication specifies that the data will not be returned within the latency of the memory” in lines 12-13. Claims 2-10 are rejected for failing to alleviate the rejection of claim 1 above. Claim 6 recites the limitation “the hazard circuit is configurable to: track a predetermined number of outstanding load instructions; and determine whether to stall the execution of the second instruction further based on whether the load instruction exceeds the predetermined number of outstanding load instructions” in lines 1-4. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to what it means for an instruction (which is not itself a number) to “exceed[]” a predetermined number. Claim 6 recites the limitation “determine whether to stall the execution of the second instruction further based on whether the load instruction exceeds the predetermined number of outstanding load instructions” in lines 3-4. However, it is indefinite as to whether the “further” is intended to convey that there is an “initial” stalling and a “further” stalling, or whether the “further” is intended to convey a further condition for stalling. Claim 11 recites the limitation “the set of pipeline stages” in line 8. However, there is insufficient antecedent basis for this limitation in the claims. Claim 11 recites the limitation “receive, from the first memory, an indication of whether the set of data will be returned within the latency of the first memory” in lines 12-13. However, it is indefinite as to how the set of data can be returned within a latency of the first memory. Also note that the limitation “based on whether the set of data will be returned within the latency of the first memory” is recited in claim 11, lines 14-15. Also see the limitation “the set of data will not be returned within the latency of the first memory” in claim 12, lines 3-4. Claim 11 recites the limitation “a same location” in line 20. However, it is indefinite as to whether this same location is the same as, or different from, “a same location” as recited in claim 11, lines 16-17. Claims 12-14 are rejected for failing to alleviate the rejections of claim 11 above. Claim 12 recites the limitation “The device of claim 11, wherein the hazard circuit is configurable to stall the second instruction based on…” in lines 1-2. However, it is indefinite as to whether this limitation (which does not recite “execution of”) is further limiting the limitation “a hazard circuit … configurable to: … determine whether to stall execution of the second instruction based on…” in claim 11, lines 8-15. Claim 13 recites the limitation “the hazard circuit is configurable to: track a predetermined number of outstanding load instructions; and stall the execution of the second instruction further when the load instruction exceeds the predetermined number of outstanding load instructions” in lines 1-4. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to what it means for an instruction (which is not itself a number) to “exceed[]” a predetermined number. Claim 13 recites the limitation “stall the execution of the second instruction further when the load instruction exceeds the predetermined number of outstanding load instructions” in lines 304. However, it is indefinite as to whether the “further” is intended to convey that there is an “initial” stalling and a “further” stalling, or whether the “further” is intended to convey a further condition for stalling. Claim 14 recites the limitation “hazard circuit” in line 1. However, it is indefinite as to whether this hazard circuit is the same as, or different from, “hazard circuit” as recited in claim 11, line 8. Claim 15 recites the limitation “a second instruction” in line 4. It is indefinite as to whether the claim implicitly requires or does not implicitly require a first instruction. Claim 15 recites the limitation “receiving, from a memory, an indication of whether a set of data will be received within a latency period of the memory” in lines 2-3. However, it is indefinite as to how data can be received within a latency period of the memory. Claims 16-20 are rejected for failing to alleviate the rejections of claim 15 above. Claim 16 recites the limitation “the latency period associated with the set of data” in line 3. However, there is insufficient antecedent basis for this limitation in the claims. Claim 19 recites the limitation “the determining of whether to stall the second instruction is further based on whether a load instruction associated with the set of data exceeds a predetermined number of outstanding load instructions” in lines 1-4. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to what it means for an instruction (which is not itself a number) to “exceed[]” a predetermined number. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Note that prior art references which were either relied upon in prior art rejections during the examination of the parent applications (i.e., Akkary, Zaidi, Rozas, Trauben, Arnold, Anderson, Wang, relied upon in one or more of 18/487,186; 17/688,260; and 16/685747) or separately cited as pertinent with their relevance to the claims explained during the examination of the parent applications (see page 26 in the office action dated January 6, 2021, of parent application 16/685747, and pages 23-24 in the office action dated May 22, 2024, of parent application 18/487186, in the latter case) are pertinent to the instant application for the same reasons and have been listed in the Information Disclosure Statement filed February 10, 2025, in the instant application. Tune et al. (US 20140372696 A1) disclose hazard detection circuitry for detecting and addressing read-after-write hazards or write-after-write hazards to ensure correct processing results (see paragraph [0068]), which is relevant to the claimed hazard circuit. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH E VICARY whose telephone number is (571)270-1314. The examiner can normally be reached Monday to Friday, 9:00 AM to 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571)270-3995. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEITH E VICARY/Primary Examiner, Art Unit 2183 Application/Control Number: 19/049,097 Page 2 Art Unit: 2183 Application/Control Number: 19/049,097 Page 4 Art Unit: 2183 Application/Control Number: 19/049,097 Page 5 Art Unit: 2183 Application/Control Number: 19/049,097 Page 6 Art Unit: 2183 Application/Control Number: 19/049,097 Page 7 Art Unit: 2183 Application/Control Number: 19/049,097 Page 8 Art Unit: 2183 Application/Control Number: 19/049,097 Page 10 Art Unit: 2183 Application/Control Number: 19/049,097 Page 11 Art Unit: 2183 Application/Control Number: 19/049,097 Page 14 Art Unit: 2183 Application/Control Number: 19/049,097 Page 15 Art Unit: 2183 Application/Control Number: 19/049,097 Page 16 Art Unit: 2183
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