Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1 – 12 are presented for examination.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/04/2026 was received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract of the disclosure is objected to because the language “while maintaining the same or fewer redundancy bits compared to conventional error correction codes” is a purported merit and therefore the abstract of the disclosure fails to provide a concise statement of the technical disclosure of the patent.
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the limitation “read out modified data where the encoded data has been modified by operating environment” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “read out”. Specifically, the examiner has interpreted “data has been modified by operating environment” as data that contains and error (paragraph 0041). The Examiner asserts errors in data is unpredictable. One of ordinary skill in the art would be unclear how to “read out modified data” when the modification (error) can only be detected after the “read out”.
Regarding claim 1, the limitation “correct single or multiple errors within a single cell of the modified data” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear scope of data organized as a single cell. Specifically, if a cell is a logical or physical partitioning of data.
Regarding claim 5, the limitation “read out modified data where the encoded data has been modified by operating environment” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “read out”. Specifically, the examiner has interpreted “data has been modified by operating environment” as data that contains and error (paragraph 0041). The Examiner asserts errors in data is unpredictable. One of ordinary skill in the art would be unclear how to “read out modified data” when the modification (error) can only be detected after the “read out”.
Regarding claim 5, the limitation “correct single or multiple errors within a single cell of the modified data” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear scope of data organized as a single cell. Specifically, if a cell is a logical or physical partitioning of data.
Regarding claim 9, the limitation “read out modified data where the encoded data has been modified by operating environment” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “read out”. Specifically, the examiner has interpreted “data has been modified by operating environment” as data that contains and error (paragraph 0041). The Examiner asserts errors in data is unpredictable. One of ordinary skill in the art would be unclear how to “read out modified data” when the modification (error) can only be detected after the “read out”.
Regarding claim 9, the limitation “correct single or multiple errors within a single cell of the modified data” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear scope of data organized as a single cell. Specifically, if a cell is a logical or physical partitioning of data.
Any claim not addressed above is rejected due to its dependency on a rejected claim
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticpated by Regev et al., U.S. Publication 2007/0168777 (herein Regev).
Regarding claim 1, Regev discloses: A semiconductor chip for correcting errors (abstract), comprising: an encoder logic circuit configured to acquire data and encode the acquired data by multiplying a pre-generated error correction code's generator matrix with the acquired data (paragraph 0031; figure 2); a memory configured to receive encoded data, store two or more bits of data in one memory cell, and read out modified data where the encoded data has been modified by operating environment (claim 60); and a logic circuit configured to acquire the modified data and correct single or multiple errors within a single cell of the modified data using the error correction code's parity check matrix (claim 60).
Regarding claim 5, Regev discloses: A semiconductor system for correcting errors (abstract), comprising: a memory chip configured to receive encoded data, store two or more bits of data in one memory cell, and read out modified data where the encoded data has been modified by the memory's operating environment (figure 4; claim 60); a control chip configured to control the memory chip, wherein the control chip includes: an encoder logic circuit configured to acquire data and encode the acquired data by multiplying a pre-generated error correction code's generator matrix with the acquired data and store the encoded data in the memory chip (paragraph 0031; figure 2); and a logic circuit configured to acquire the modified data from the memory chip and correct single or multiple errors within a single cell of the modified data using the error correction code's parity check matrix (claim 60).
Regarding claim 9, Regev discloses: A semiconductor chip for correcting errors (abstract), comprising: a transceiver configured to receive modified data where data and encoded data have been modified through communication, and transmit encoded data and decoded data (figure 4; claim 60); an encoder logic circuit configured to multiply the data with a pre-generated error correction code's generator matrix to generate the encoded data (paragraph 0031; figure 2); and a logic circuit configured to correct single or multiple errors within a single cell boundary of the modified data using the error correction code's parity check matrix (claim 60).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, 6, 7, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Regev, in view of Applicant Admitted Prior Art (herein AAPA).
Regarding claim 2, Regev teaches the limitations of the parent claim. Regev does not explicitly teach: for 4LC memory, the error correction code has 64 bits of original data bits and 7 check bits, and is configured to correct single or double errors within a single cell.
AAPA teaches: 4LC Memory, single error correction-double error detection, single error correction-double adjacent error correction, and single error correction-double adjacent error correction-triple adjacent error correction (paragraph 0003 – 0007).
One of ordinary skill in the art, at the time of the effective filing date of the invention, would find it obvious to combine the teaching of Regev: a logic circuit configured to acquire the modified data and correct single or multiple errors within a single cell of the modified data using the error correction code's parity check matrix; with the teaching of AAPA: 4LC memory and error correction code for the purpose of protecting multi-level memory (paragraph 0003). 4LC/ 8LC and other multi-level memories are well-known in the art (paragraph 0003). A data width of 64 bits is well-known design choice in the art. A number of check bits is well-known design choice in the art. Data width and the number of check bits is a well-known design choice to determine the level of data protection in the system. The values disclosed would be obvious to try. One of ordinary skill in the art would recognize the use of well-known design choice would yield a predictable result.
Regarding claim 3, Regev teaches the limitations of the parent claim. Regev does not explicitly teach: wherein for 8LC memory, the error correction code has 64 bits of original data bits and 8 check bits, and is configured to correct single, double, or triple errors within a single cell.
AAPA teaches: wherein for 8LC memory, the error correction code has 64 bits of original data bits and 8 check bits, and is configured to correct single, double, or triple errors within a single cell (paragraph 0003). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 6, Regev teaches the limitations of the parent claim. Regev does not explicitly teach: for 4LC memory, the error correction code has 64 bits of original data bits and 7 check bits, and is configured to correct single or double errors within a single cell.
AAPA teaches: 4LC Memory, single error correction-double error detection, single error correction-double adjacent error correction, and single error correction-double adjacent error correction-triple adjacent error correction (paragraph 0003 – 0007). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 7, Regev teaches the limitations of the parent claim. Regev does not explicitly teach: wherein for 8LC memory, the error correction code has 64 bits of original data bits and 8 check bits, and is configured to correct single, double, or triple errors within a single cell.
AAPA teaches: wherein for 8LC memory, the error correction code has 64 bits of original data bits and 8 check bits, and is configured to correct single, double, or triple errors within a single cell (paragraph 0003). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 10, Regev teaches the limitations of the parent claim. Regev does not explicitly teach: for 4LC memory, the error correction code has 64 bits of original data bits and 7 check bits, and is configured to correct single or double errors within a single cell.
AAPA teaches: 4LC Memory, single error correction-double error detection, single error correction-double adjacent error correction, and single error correction-double adjacent error correction-triple adjacent error correction (paragraph 0003 – 0007). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Regarding claim 11, Regev teaches the limitations of the parent claim. Regev does not explicitly teach: wherein for 8LC memory, the error correction code has 64 bits of original data bits and 8 check bits, and is configured to correct single, double, or triple errors within a single cell.
AAPA teaches: wherein for 8LC memory, the error correction code has 64 bits of original data bits and 8 check bits, and is configured to correct single, double, or triple errors within a single cell (paragraph 0003). And in view of the motivation previously stated above, for claim 1, the claim is rejected.
Allowable Subject Matter
Claims 4, 8, and 12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kanazawa; Keisuke et al. US 7096406 B2
Lee; Myungkyu et al. US 20240185942 A1
CHA; Sang-Uhn et al. US 20170109231 A1
Asnaashari; Mehdi US 9524210 B1
CHUNG; Bi Woong et al. US 20220269560 A1
Yang; Joon Sung et al. US 10860252 B2
an encoder logic circuit configured to acquire data and encode the acquired data by multiplying a pre-generated error correction code's generator matrix with the acquired data;
a memory configured to receive encoded data, store two or more bits of data in one memory cell, and read out modified data where the encoded data has been modified by operating environment;
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111
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