DETAILED ACTION
This action is responsive to the following communications: the Application filed on February 10, 2025, the Foreign Priority papers retrieved on February 21, 2024, and the Information Disclosure Statement filed on February 10, 2025.
Claims 1-6 are pending. Claims 1-2 and 4-5 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on February 10, 2025. This IDS has been considered.
Drawings
The drawings are objected to because all of the Figures filed on February 10, 2025 are degraded and blurry, showing dotted lines and dotted lettering and numbering, which may indicate applicant submitted Figures that were in greyscale. Applicant is reminded that solid lines used in the Drawings must be uniformly thick, black, and solid and the words and labels in the Drawings must be plain and legible. MPEP 608.02(f)(V).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0022], line 6, “defects of the instructions cache logic circuit” should be --defects of the instruction cache logic circuit--.
In paragraph [0064], line 2, “some or all the instruction stored” should be --some or all the instructions stored--.
In paragraph [0110], line 6, “the current counter value (ValCurr)” should be --the current counter value (ValCurr1)”--.
In paragraph [0110], lines 7 and 9, “final counter value (ValFnl)” should be --final counter value (ValFnl1)--.
In paragraph [0110], line 8, “the initial counter value (ValInt1)” should be --the initial counter value (ValInit1)--.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
In claims 3 and 6, the term “means” is treated as a term that invokes means-plus-function because the limitation used the term “means” followed by functional claim language and the claim itself does not recite sufficient structure for performing the recited function. Therefore, the limitation “means forming the cache memory at the address is different from the data stored in the memory location of the second memory located at the address” is interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claims 1 and 4, each claim recites “blocking an unintended execution of instructions by the test”. The scope of “an unintended execution of instructions by the test” is unclear. First, it is unclear whether the phrase “by the test” modifies “blocking” or “execution”. The limitation may be interpreted as blocking by operation of the test, an unintended execution of instructions; or blocking an execution of instructions that is unintended by the test. Second, the claims do not provide an objective boundary for determining which instruction executions are “unintended”. For example, it is unclear whether “unintended” refers to instructions not included among the M stored instructions; instructions caused by an interrupt; instructions unrelated to the testing method; or any instruction that produces an additional increment of the cache access counter. The test necessarily executes instructions other than the M instructions, including instruction for reading the counter values, subtracting the values and performing the comparison. Thus, “unintended” cannot clearly be understood as instructions outside the sequence of M instructions. Although paragraphs [0016] and [0051]-[0055] of the disclosure describe disabling interrupts to prevent execution of additional instructions, the claims are not limited to interrupt executions. Therefore, it is unclear what execution must be blocked to satisfy the limitation. Accordingly, claims 1 and 4 fail to define the metes and bounds of the claimed methods with reasonable clarity.
With respect to claims 2 and 5, each claim recites “reading at least one of a first initial counter value of a cache access counter or a second initial counter value of a cache failure counter” and subsequently recites “reading at least one of a first final counter value of the cache access counter or a second final value of the cache failure counter”. The claims independently disclose selection of either initial value and either final value. The language does not require the selected initial value and selected final value to be values of the same counter. For example, the claims appear to comprise reading only the first initial value of the cache access counter and reading only the second final value of the cache failure counter. Under that selection, neither a complete cache access counter pair nor a complete cache failure counter pair is available for the subsequently recited subtraction. Therefore, it is unclear whether the claims require the initial and final values of the cache access counter; the initial and final values of the cache failure counter; both corresponding pairs; or any independently selected initial and final values.
Claims 2 and 5 further recite “blocking a data reading unintended by the test”. This phrase does not provide an objective boundary for distinguishing an unintended data reading from an intended data reading. Although paragraphs [0025] and [0087]-[091] of the disclosure describe data readings caused by interruptions, the claims are not limited to interrupt data readings. Therefore, it is unclear what data reading must be blocked to satisfy the limitation. Accordingly, claims 2 and 5 fail to define the metes and bounds of the claimed methods with reasonable clarity.
With respect to claims 3 and 6, claims 3 and 6 depend on claims 2 and 5, respectively, and incorporate all limitations of claims 2 and 5. Therefore, claims 3 and 6 are indefinite for at least the same reason identified above with respect to claims 2 and 5. Claims 3 and 6 additionally recite “data read in the means forming the cache memory”. The phrase “the means forming the cache memory” lacks proper antecedent basis. Neither claims 3 and 6 nor independent claims 2 and 5 previously introduce “a mean forming the cache memory”. Therefore, the absence of antecedent basis renders the scope of claims 3 and 6 indefinite.
Claims 3 and 6 are additionally rejected under 35 U.S.C. 112(b) because the limitation “means forming the cache memory” is interpreted under 35 U.S.C. 112(f) and the specification fails to disclose sufficient corresponding structure for performing the claimed function of forming the cache memory. The specification identifies a data cache logic circuit “LcacheB” only as a functional block; however, paragraph [0074] states that “the structure and the operation of such a logic circuit LcacheB are classic and will not therefore be detailed in the present application”. Accordingly, the specification fails to disclose sufficient corresponding structure to the entire claimed function.
Allowable Subject Matter
Claims 1-6 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to independent claim 1, the closest prior art, Tsuboi (US 20060190686), which shows in Figure 1 a cache circuit 100 for supporting examination of a system bus by executing a loop structured program whose instructions may be stored in an instruction cache, counting instruction cache hits and instruction accesses using respective counters, calculating a cache hit rate from those counts, comparing the cache hit rate or hit count with a predetermined threshold and disabling cache entries when the threshold is exceeded so that subsequent instructions are retrieved from main memory [para. 38-51, 83 and 88]. However, Tsuboi does not teach or suggest testing an instruction cache logic circuit of an integrated circuit, comprising: storing in the cache logic circuit a sequence of instructions including M instructions; reading an initial counter value of a cache access counter; executing the sequence of instructions N times, with N being greater than or equal to 1, and, for each instruction executed from the cache logic circuit, incrementing a current counter value of the counter; reading a final counter value of the counter; blocking an unintended execution of instructions by the test for a period lasting from reading the initial counter value until reading the final counter value; subtracting the initial counter value from the final counter value; and comparing a result of the subtraction with a value equal to the product of N and M.
Thus, there is no teaching or suggestion in the prior art of record to provide the recited testing an instruction cache logic circuit of an integrated circuit, comprising: storing in the cache logic circuit a sequence of instructions including M instructions; reading an initial counter value of a cache access counter; executing the sequence of instructions N times, with N being greater than or equal to 1, and, for each instruction executed from the cache logic circuit, incrementing a current counter value of the counter; reading a final counter value of the counter; blocking an unintended execution of instructions by the test for a period lasting from reading the initial counter value until reading the final counter value; subtracting the initial counter value from the final counter value; and comparing a result of the subtraction with a value equal to the product of N and M.
With respect to independent claim 2, similar to the reasons for independent claim 1, there is no teaching or suggestion in the prior art of record to provide the recited the method comprising: storing in at least one memory location of the second memory at least one piece of data; storing a sequence of instructions in the first memory, the sequence of instructions including at least one instruction for storing in the cache logic circuit an address of the at least one memory location and corresponding data stored at the memory location and at least one instruction for reading addresses and data of the data cache logic circuit; reading at least one of a first initial counter value of a cache access counter or a second initial counter value of a cache failure counter; executing the sequence of instructions N times, with N greater than or equal to 1, and, for each store instruction and each read instruction, performing at least one of: incrementing a current counter value of the cache access counter when one of the addresses read in the cache logic circuit corresponds to the address of the at least one memory location of the second memory; or incrementing a current counter value of the cache failure counter when none of the addresses read in the cache logic circuit corresponds to the address of the at least one memory location of the second memory; reading at least one of a first final counter value of the cache access counter or a second final value of the cache failure counter; blocking a data reading unintended by the test for a period lasting from reading the first initial counter value or the second initial counter value until reading the first final counter value or the second final counter value, performing at least one of: subtracting the first initial counter value from the first final counter value of the cache access counter to obtain a first result; or subtracting the second initial counter value from the second final counter value of the cache failure counter to obtain a second result; and comparing the first result with at least one of a value equal to N times the number of read instructions contained in the sequence of instructions or the second result with a value equal to 0.
With respect to independent claim 4, similar to the reasons for independent claim 1, there is no teaching or suggestion in the prior art of record to provide the recited testing an instruction cache logic circuit of an integrated circuit, comprising: storing in the cache logic circuit a sequence of instructions including M instructions; reading an initial counter value of a cache access counter; executing the sequence of instructions N times, with N being greater than or equal to 1, and, for each instruction executed from the cache logic circuit, incrementing a current counter value of the counter; reading a final counter value of the counter; blocking an unintended execution of instructions by the test for a period lasting from reading the initial counter value until reading the final counter value; subtracting the initial counter value from the final counter value; and comparing a result of the subtraction with a value equal to the product of N and M.
With respect to independent claim 5, similar to the reasons for independent claim 1, there is no teaching or suggestion in the prior art of record to provide the recited the method comprising: storing in at least one memory location of the second memory at least one piece of data; storing a sequence of instructions in the first memory, the sequence of instructions including at least one instruction for storing in the cache logic circuit an address of the at least one memory location and corresponding data stored at the memory location and at least one instruction for reading addresses and data of the data cache logic circuit; reading at least one of a first initial counter value of a cache access counter or a second initial counter value of a cache failure counter; executing the sequence of instructions N times, with N greater than or equal to 1, and, for each store instruction and each read instruction, performing at least one of: incrementing a current counter value of the cache access counter when one of the addresses read in the cache logic circuit corresponds to the address of the at least one memory location of the second memory; or incrementing a current counter value of the cache failure counter when none of the addresses read in the cache logic circuit corresponds to the address of the at least one memory location of the second memory; reading at least one of a first final counter value of the cache access counter or a second final value of the cache failure counter; blocking a data reading unintended by the test for a period lasting from reading the first initial counter value or the second initial counter value until reading the first final counter value or the second final counter value, performing at least one of: subtracting the first initial counter value from the first final counter value of the cache access counter to obtain a first result; or subtracting the second initial counter value from the second final counter value of the cache failure counter to obtain a second result; and comparing the first result with at least one of a value equal to N times the number of read instructions contained in the sequence of instructions or the second result with a value equal to 0.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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