DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. If Applicant fails to provide a sufficiently descriptive title, Examiner will do so upon allowance of the claims.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “the first scan signal includes a first active period which overlaps the first period and the second period” (see claim 4) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-10, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han (US 2014/0307010).
Regarding claim 1, Han discloses a display device comprising: a display panel including a pixel (abstract, figs. 2-4, ¶ 56-57);
a data driver which supplies a data voltage to the pixel (figs. 2-4, ¶ 56-62, data driver 30);
and a gate driver which supplies a first scan signal and a second scan signal to the pixel (figs. 2-4, ¶ 56-65, scan driver 20 and compensation control driver 60),
wherein the pixel includes: a light emitting element (figs. 2-4, ¶ 75, ¶ 84, OLED1);
a first transistor connected between the light emitting element and a first power line (figs. 2-4, ¶ 63, ¶ 83, TD1; see also fig. 8);
a second transistor connected to the first transistor, wherein the second transistor receives the data voltage and the first scan signal (figs. 2-4, ¶ 79, TR3 transmits data voltage according to control signal GW; see also fig. 8);
and a third transistor connected to a control electrode of the first transistor, wherein the third transistor receives the second scan signal (figs. 2-4, ¶ 82, TR5 receives control signal GC; see also fig. 8),
wherein the data driver supplies the data voltage to the pixel during a first period of a frame and supplies a bias voltage to the pixel during a second period of the frame (figs. 3-5, ¶ 68-69, ¶ 97-98, e.g., TR3 turned on at time P7 to provide data voltage to driving transistor; see also ¶ 108-112, bias period at P11; see also figs. 8-9, ¶ 150-152, data signals are transmitted as particular bias voltages Vbias in bias period 5),
and wherein the second scan signal includes a second active period overlapping the first period and a compensation active period overlapping the second period (figs. 3-5, GC on [low] at periods 2 and 5, see ¶ 92-98, ¶ 111-112; see also figs. 8-9).
Regarding claim 2, Han discloses wherein the compensation active period has a duration equal to a duration of the second active period (fig. 5, GC on [low] at periods 2 and 5, see ¶ 92-98, ¶ 111-112).
Regarding claim 4, Han discloses wherein the first scan signal includes a first active period which overlaps the first period and the second period, and wherein the first active period has a duration shorter than a duration of the second active period (figs. 8-9, ¶ 143-152, GW applied during periods 2 and 5, first GW pulse shorter than overlapping GC pulse).
Regarding claim 5, Han discloses wherein the first active period includes a first sub-active period overlapping the second active period or the compensation active period (figs. 8-9, ¶ 143-152, GW applied during period 2 overlapping GC pulse),
and a second sub-active period not overlapping the second active period or the compensation active period (figs. 8-9, ¶ 143-152, GW applied during period 5 not overlapping GC pulse of period 2).
Regarding claim 6, Han discloses wherein a start time point of the first sub-active period follows a start time point of the second active period, and wherein a start time point of the second sub-active period follows an end time point of the second active period (figs. 8-9, ¶ 143-152, GW applied during periods 2 and 5, first GW pulse starts after start of overlapping GC pulse).
Regarding claim 7, Han discloses wherein the second transistor includes: a first electrode connected to a data line; a second electrode connected to a first electrode of the first transistor; and a control electrode which receives the first scan signal (figs. 2-4, ¶ 79, TR3 transmits data voltage according to control signal GW; see also fig. 8),
and wherein the third transistor includes: a first electrode connected to the control electrode of the first transistor; a second electrode connected to a second electrode of the first transistor; and a control electrode which receives the second scan signal (figs. 2-4, ¶ 82, TR5 receives control signal GC; see also fig. 8).
Regarding claim 8, Han discloses wherein the gate driver further supplies a third scan signal to the pixel, and wherein the pixel further includes: a fourth transistor including a first electrode connected to the control electrode of the first transistor, a second electrode connected to an initialization voltage line, and a control electrode which receives the third scan signal (figs. 2-4, ¶ 61-65, ¶ 78, TR2 receives scan signal; see also fig. 8).
Regarding claim 9, Han discloses a light emitting driver which applies an emission control signal to the pixel (figs. 2-4, ¶ 63, ¶ 88, power controller provides ELVSS, ELVDD signals; see also figs. 8-9).
Regarding claim 10, Han discloses wherein the emission control signal includes a first inactive period and a second inactive period which overlap the first period and the second period, respectively, and wherein the second active period and the compensation active period overlap the first inactive period and the second inactive period, respectively (fig. 5, ¶ 93, ¶ 107-111, e.g., ELVSS changes to high level at periods 2 and 5; see also fig. 9).
Regarding claim 16, Han discloses an electronic device comprising: a display device which provides an image, comprising: a display panel including a pixel which displays an image during a plurality of frames (abstract, figs. 2-4, ¶ 56-57);
a data driver which supplies a data voltage to the pixel (figs. 2-4, ¶ 56-62, data driver 30);
a gate driver which supplies a first scan signal and a second scan signal to the pixel (figs. 2-4, ¶ 56-65, scan driver 20 and compensation control driver 60);
and a driving controller which receives an image signal and a control signal, and controls operations of the data driver and the gate driver (figs. 2-4, ¶ 56-66, timing controller 40),
wherein the pixel includes: a light emitting element (figs. 2-4, ¶ 75, ¶ 84, OLED1);
a first transistor connected between the light emitting element and a first power line (figs. 2-4, ¶ 63, ¶ 83, TD1; see also fig. 8);
a second transistor connected to the first transistor, wherein the second transistor receives the data voltage and the first scan signal (figs. 2-4, ¶ 79, TR3 transmits data voltage according to control signal GW; see also fig. 8);
and a third transistor connected to a control electrode of the first transistor, wherein the third transistor receives the second scan signal (figs. 2-4, ¶ 82, TR5 receives control signal GC; see also fig. 8),
wherein each of the plurality of frames includes a first period and a plurality of second periods (figs. 3-5, ¶ 68-69, ¶ 97-98, e.g., TR3 turned on at time P7 to provide data voltage to driving transistor; see also ¶ 108-112, e.g., first and second half of bias period 5 considered plurality of second periods; see also figs. 8-9, ¶ 150-152, data signals are transmitted as particular bias voltages Vbias in bias period 5),
wherein the data driver supplies the data voltage to the pixel during the first period and supplies a bias voltage to the pixel during the plurality of second periods (figs. 3-5, ¶ 68-69, ¶ 97-98, e.g., TR3 turned on at time P7 to provide data voltage to driving transistor; see also ¶ 108-112, e.g., first and second half of bias period 5; see also figs. 8-9, ¶ 150-152, data signals are transmitted as particular bias voltages Vbias in bias period 5),
and wherein the second scan signal includes a second active period overlapping the first period and a compensation active period overlapping at least one of the plurality of second periods (figs. 3-5, GC on [low] at periods 2 and 5, see ¶ 92-98, ¶ 111-112; see also figs. 8-9).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Jeong et al. (US 2023/0274690).
Regarding claim 3, Han fails to explicitly disclose wherein the compensation active period includes a plurality of sub-compensation active periods, and wherein each of the sub-compensation active periods has a duration equal to a duration of the second active period.
Jeong teaches wherein the compensation active period includes a plurality of sub-compensation active periods, and wherein each of the sub-compensation active periods has a duration equal to a duration of the second active period (fig. 5, ¶ 112-115, GC active multiple times during C2).
Han and Jeong are both directed to driving circuits for LED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Han with the device of Jeong since such a modification minimizes a change in luminance due to hysteresis characteristics of the driving transistor (Jeong, ¶ 130, ¶ 187) and the threshold voltage compensation time of the driving transistor may be sufficiently secured (Jeong, ¶ 185).
Claims 11-15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Seo et al. (US 2021/0407352).
Regarding claim 11, Han fails to explicitly disclose wherein the gate driver includes: a first scan circuit which outputs the first scan signal; and a second scan circuit which outputs the second scan signal.
Seo teaches wherein the gate driver includes: a first scan circuit which outputs the first scan signal (figs. 7-8, ¶ 115-118, ¶ 129-147, e.g., scan driving circuit with masking circuit MSC1);
and a second scan circuit which outputs the second scan signal (figs. 7-8, ¶ 115-118, ¶ 129-147, e.g., scan driving circuit with masking circuit MSC2).
Han and Seo are both directed to driving circuits for LED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Han with the device of Seo since such a modification provides high operation speed (Seo, ¶ 2), reduces power consumption (Seo, ¶ 201), and provides masking of the first and second signals (Seo, ¶ 117).
Regarding claim 12, Seo further teaches wherein the gate driver further includes: a masking circuit connected to an output terminal of the second scan circuit to receive the second scan signal, wherein the masking circuit selectively masks an output of the second scan signal in response to a masking signal (figs. 7-8, ¶ 115-118, ¶ 129-147, e.g., scan driving circuit with masking circuit MSC2).
Regarding claim 13, Han discloses wherein the display panel displays an image during a plurality of frames, wherein each of the plurality of frames includes the first period and the second period (figs. 3-5, ¶ 68-69, ¶ 97-98; see also ¶ 108-112; see also figs. 8-9, ¶ 150-152).
Seo further teaches wherein the masking circuit masks the output of the second scan signal during the second period in response to the masking signal in units of k preset frames, wherein k is an integer equal to or greater than 2 (figs. 7-8, ¶ 115-118, ¶ 129-147; see also ¶ 77 and table 1, driving frequencies may be multiples of a normal frequency).
Regarding claim 14, Han discloses wherein the gate driver further includes: a scan circuit which outputs a scan signal through an output terminal thereof (figs. 2-4, ¶ 56-65, scan driver 20 and compensation control driver 60).
Han fails to disclose a switching circuit which receives the scan signal, outputs the scan signal as the first scan signal and the second scan signal during the first period, and outputs the scan signal as the second scan signal during the second period.
Seo further teaches a switching circuit which receives the scan signal, outputs the scan signal as the first scan signal and the second scan signal during the first period, and outputs the scan signal as the second scan signal during the second period (figs. 7-8, ¶ 115-118, ¶ 129-147, e.g., masking circuits MSC1 and MSC2; first and second scan signals output at high or low levels based on masking signals).
Han and Seo are both directed to driving circuits for LED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Han with the device of Seo since such a modification provides high operation speed (Seo, ¶ 2), reduces power consumption (Seo, ¶ 201), and provides masking of the first and second signals (Seo, ¶ 117).
Regarding claim 15, Seo further teaches wherein the switching circuit includes: a first switching element connected to the output terminal to receive the scan signal, turned on during the first period in response to a first switching signal to output the scan signal as the first scan signal, and turned off during the second period not to output the first scan signal (figs. 7-8, ¶ 115-118, ¶ 129-147, e.g., masking circuit MSC1; first scan signal output at high or low levels based on masking signals);
and a second switching element connected to the output terminal to receive the scan signal, and turned on during the first period and the second period in response to a second switching signal to output the scan signal as the second scan signal (figs. 7-8, ¶ 115-118, ¶ 129-147, e.g., masking circuit MSC2; second scan signal output at high or low levels based on masking signals).
Regarding claim 17, this claim is rejected under the same rationale as claim 11.
Regarding claim 18, this claim is rejected under the same rationale as claim 12.
Regarding claim 19, Seo further teaches wherein the masking circuit outputs the second scan signal during at least one second period selected from the plurality of second periods in response to the masking signal, and masks the second scan signal in a way such that the second scan signal is not output during remaining second periods (figs. 7-8, ¶ 115-118, ¶ 129-147, e.g., masking circuit MSC2; second scan signal output at high or low levels based on masking signals).
Claims 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Liu et al. (US 2022/0208087).
Regarding claim 20, Han discloses a display device comprising: a display panel including a pixel (abstract, figs. 2-4, ¶ 56-57);
a data driver which supplies a data voltage to the pixel (figs. 2-4, ¶ 56-62, data driver 30);
and a gate driver which supplies a first scan signal and a second scan signal to the pixel (figs. 2-4, ¶ 56-65, scan driver 20 and compensation control driver 60),
wherein the pixel includes: a light emitting element (figs. 2-4, ¶ 75, ¶ 84, OLED1);
a first transistor connected between the light emitting element and a first power line (figs. 2-4, ¶ 63, ¶ 83, TD1; see also fig. 8);
a second transistor connected to the first transistor, wherein the second transistor receives the data voltage and the first scan signal (figs. 2-4, ¶ 79, TR3 transmits data voltage according to control signal GW; see also fig. 8);
and a third transistor connected to a control electrode of the first transistor, wherein the third transistor receives the second scan signal (figs. 2-4, ¶ 82, TR5 receives control signal GC; see also fig. 8),
wherein the data supplies the data voltage to the pixel during a first period and supplies a bias voltage to the pixel during a second period (figs. 3-5, ¶ 68-69, ¶ 97-98, e.g., TR3 turned on at time P7 to provide data voltage to driving transistor; see also ¶ 108-112, bias period at P11; see also figs. 8-9, ¶ 150-152, data signals are transmitted as particular bias voltages Vbias in bias period 5),
wherein each of the first period and the second period includes a valid period (figs. 3-5, ¶ 68-69, ¶ 97-98, e.g., periods 2-5; see also ¶ 108-112, see also figs. 8-9, ¶ 150-152),
and wherein the second scan signal includes a second active period overlapping the valid period of the first period, and a compensation active period (figs. 3-5, GC on [low] at periods 2 and 5, see ¶ 92-98, ¶ 111-112; see also figs. 8-9).
Han fails to disclose a front porch period preceding the valid period, and a back porch period following the valid period, and a compensation active period overlapping at least one selected from the back porch period of the first period and the front porch period of the second period.
Liu teaches a front porch period preceding the valid period, and a back porch period following the valid period (fig. 8, ¶ 67-68, e.g., first and second half of porch period),
and a compensation active period overlapping at least one selected from the back porch period of the first period and the front porch period of the second period (fig. 8, ¶ 67-68, threshold capture during porch period).
Han and Liu are both directed to driving circuits for LED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Han with the device of Liu since such a modification improves refresh rate and improves display effect (Liu, ¶ 67).
Regarding claim 21, this claim is rejected under the same rationale as claim 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: See attached Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH L CRAWLEY whose telephone number is (571)270-7616. The examiner can normally be reached Monday - Friday 10-6 ET.
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/KEITH L CRAWLEY/ Primary Examiner, Art Unit 2626
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