DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 3-30 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 and 12-22 of U.S. Patent No. 12,241,932. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the ‘932 patent recite at least the limitations of the present claims and thus read on the present claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 27 recites the limitation "the second computer instruction". There is insufficient antecedent basis for this limitation in the claim. It is assumed Applicant intended claim 27 to depend from claim 26.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-7, 16-20, and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Pat. 5,892,906; hereinafter referred to as Chou) in view of Kroening et al (US Pat. Pub. 2004/0083208; hereinafter referred to as Kroening).
As per claim 1:
Chou teaches a method of testing semiconductor circuits, comprising:
loading, into an internal memory of the semiconductor circuit (Fig. 1, 15), first computer instructions comprising boot code (Fig. 3, 22), a basic input/output system (BIOS) (Fig. 3; col. 2, lines 63-65), and a functional test (Fig. 2, 23; col. 3, line 64); and
operating the semiconductor circuit in a test boot mode, the operating including executing the boot code, portions of the BIOS, and the functional test (Fig. 10).
Not explicitly disclosed is attaching a semiconductor circuit to a test bed. However, Kroening in an analogous art teaches loading a test routine into memory of a test bed comprising a motherboard (paragraph 22; Fig. 1A, 40).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to use the motherboard of the system of Chou as a test bed. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Chou already teaches a motherboard (col. 3, lines 30-33), and Kroening suggests that a motherboard can be used as a test bed to perform test operations such as the self-test taught by Chou.
As per claims 4, 17: Chou teaches the method of claim 1 and semiconductor die of claim 16, further comprising loading, into the internal memory of the semiconductor circuit, an operating system (OS) (col. 3, lines 46-47).
As per claims 5, 18: Chou teaches the method of claim 4 and semiconductor die of claim 17, wherein operating the operating the semiconductor circuit in a test boot mode further comprises operating portions of the OS (col. 3, lines 44-47).
As per claims 6, 19: Chou teaches the method of claim 1 and semiconductor die of claim 16, wherein loading first computer instructions into the internal memory of the semiconductor circuit comprises loading firmware or instructions that replace or suppress portions of the boot code (col. 3, lines 24-28; boot code is suppressed without proper authentication) that require connections to hardware other than the semiconductor circuit (Fig. 2, security key).
As per claims 7, 20:
Chou teaches the method of claim 1 and semiconductor die of claim 16, wherein the first computer instructions include one or more skip instructions for skipping one or more operations of installed firmware of the semiconductor circuit, or wherein executing the first computer instructions includes bypassing one or more operations in a boot flow as provided in installed firmware of the semiconductor circuit (col. 4, lines 61-63).
As per claim 16: Chou teaches a semiconductor die, comprising:
one or more interfaces (Fig. 1; motherboard interface);
an internal memory (Fig. 1, 15), the internal memory being loaded with first computer instructions (Fig. 3), the first computer instructions comprising boot code (Fig. 3, 22), a basic input/output system (BIOS) (Fig. 3; col. 2, lines 63-65), and a functional test (Fig. 2, 23; col. 3, line 64); and
a first processing circuit (Fig. 1, 14) configured to execute the first computer instructions thereby operating the first processing circuit in a test boot mode, the operating including executing the boot code, portions of the BIOS, and the functional test (Fig. 10).
Not explicitly disclosed is one or more interfaces configured to attach to a test bed. However, Kroening in an analogous art teaches loading a test routine into memory of a test bed comprising a motherboard (paragraph 22; Fig. 1A, 40).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to use the motherboard of the system of Chou as a test bed. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Chou already teaches a motherboard (col. 3, lines 30-33), and Kroening suggests that a motherboard can be used as a test bed to perform test operations such as the self-test taught by Chou.
As per claim 29: Chou teaches the semiconductor die of claim 16, wherein the first processing circuit includes a boot controller (Fig. 1, CPU 14).
Claim(s) 2, 3, 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Kroening in view of Ozoe et al (US Pat. Pub. 2013/0223164; hereinafter referred to as Ozoe).
As per claim 2:
Chou et al teach the method of claim 1. Not explicitly disclosed is wherein attaching the semiconductor circuit to the test bed comprises attaching a packaged semiconductor circuit to the test bed. However, Ozoe in an analogous art teaches a CPU and memory in a packaged semiconductor circuit (paragraph 60).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to form the CPU and memory components of Chou in a packaged semiconductor device. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Ozoe teaches that the components may be packaged or non-packaged without changing the principle of operation.
As per claim 3:
Chou et al teach the method of claim 1. Not explicitly disclosed is wherein attaching the semiconductor circuit to the test bed comprises attaching a non-packaged semiconductor circuit to the test bed. However, Ozoe in an analogous art teaches a CPU and memory in a non-packaged semiconductor circuit (paragraph 60).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to form the CPU and memory components of Chou in a non-packaged semiconductor device. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Ozoe teaches that the components may be packaged or non-packaged without changing the principle of operation.
As per claim 22: Chou further teaches the semiconductor die of claim 16, wherein the first computer instructions are executed to perform a functional test of the semiconductor die (Fig. 3, 23). Not explicitly disclosed is the first computer instructions being loaded and executed without the semiconductor die being attached to a die package. However, Ozoe in an analogous art teaches a CPU and memory in a non-packaged semiconductor circuit (paragraph 60).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to form the CPU and memory components of Chou in a non-packaged semiconductor device. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Ozoe teaches that the components may be packaged or non-packaged without changing the principle of operation.
Claim(s) 8, 21, and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Kroening in view of Dreyer et al (US Pat. 5,479,652; hereinafter referred to as Dreyer).
As per claims 8, 21:
Chou et al teach the method of claim 1 and semiconductor die of claim 16. Not explicitly disclosed is wherein the first computer instructions are loaded into the internal memory via a joint test action group (JTAG) interface after the semiconductor circuit is powered on. However, Dreyer in an analogous art teaches loading instructions via a joint test action group (JTAG) interface (Fig. 1, 34; col. 3, lines 49-54).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to implement a JTAG interface in the system of Chou et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because no additional pins would have been needed for running additional testing, thereby saving costs (col. 3, lines 54-46).
As per claim 30: Chou et al teach the semiconductor die of claim 16. Not explicitly disclosed is further comprising a boot pin that, when asserted, triggers the semiconductor die to enter an automatic test equipment (ATE) mode, the ATE mode including enabling input from JTAG pins. However, Dreyer in an analogous art teaches a boot pin for triggering a test mode including enabling input from JTAG pins (col. 6, lines 46-58; see also Fig. 1, 30).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to implement the test interface of Dreyer for enabling JTAG input. This modification would have been obvious for one of ordinary skill in the art at the time of filing because no additional pins would have been needed for running additional testing, thereby saving costs (col. 3, lines 54-46).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Kroening in view of Ghosh et al (US Pat. 5,598,556; hereinafter referred to as Ghosh).
As per claim 9:
Chou et al teach the method of claim 1. Not explicitly disclosed is wherein the first computer instructions are executed to perform a benchmark test of the semiconductor circuit. However, Ghosh in an analogous art teaches performing a benchmarking test of a semiconductor circuit (col. 1, lines 16-19).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to perform a CPU benchmarking test in Chou. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have been useful for improving or optimizing processor performance under various operating conditions (col. 1, lines 20-21).
Claim(s) 10, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Kroening in view of Shivanna et al (US Pat. Pub. 2017/0315818; hereinafter referred to as Shivanna).
As per claims 10, 23:
Chou et al teach the method of claim 1 and semiconductor die of claim 16. Not explicitly disclosed is further comprising logging functional errors during execution of the first computer instructions in the functional test, the functional errors including runtime errors before a system fault. However, Shivanna in an analogous art teaches logging errors in a register to detect an early boot error before a system fault (paragraph 10).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to implement the logging of Shivanna in the system of Chou et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have helped detect failures that happen in the early part of the server boot process (paragraph 7).
Claim(s) 11, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Kroening in view of Brown et al (US Pat. Pub. 2019/0095377; hereinafter referred to as Brown).
As per claims 11, 24:
Chou et al teach the method of claim 1 and semiconductor die of claim 16. Not explicitly disclosed is further comprising: logging one or more events of operating the semiconductor circuit in the test boot mode; and transmitting logs of the one or more events from the semiconductor circuit via a joint test action group (JTAG) interface or a universal asynchronous receiver/transmitter (UART) interface. However, Brown in an analogous art teaches logging error events and transmitting logs of the events via a UART terminal (paragraph 13).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to maintain and transmit error logs as taught by Brown. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have allowed an administrator to review and act on the errors, as discussed by Brown.
Claim(s) 12, 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Kroening in view of Liu et al (US Pat. Pub. 2018/0225126; hereinafter referred to as Liu).
As per claims 12, 25:
Chou et al teach the method of claim 1 and semiconductor die of claim 16. Not explicitly disclosed is wherein the first computer instructions include a Unified Extensible Firmware Interface (UEFI) BIOS, firmware, or a combination thereof. However, Liu in an analogous art teaches a UEFI BIOS (paragraph 9).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to use a UEFI BIOS as the bios of Chou. This modification would have been obvious for one of ordinary skill in the art at the time of filing because UEFI was well-known and used interchangeably with BIOS, as explained by Liu in paragraph 9.
Allowable Subject Matter
Claims 13-15 and 26-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art teach the limitations of parent claims 1 and 16 as detailed above. However, none of the prior art teach or fairly suggest: bringing a first semiconductor circuit of the semiconductor circuit out of reset via the executing of the first computer instructions; loading second computer instructions into the internal memory; and executing the second computer instructions on the semiconductor circuit, as recited in claim 13, particularly in combination with each and every element of the parent claim. Claim 26 would be allowable for analogous reasons. Claims 14, 15, 27, and 28 depend from the claims above and would be allowable for at least the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111
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