DETAILED ACTION
This Non-final action is responsive to the following communications: application filed on 02/10/2025.
Claims 1-20 are pending. Claims 1, 11, and 18 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04, Breadth of a claim is not to be equated with indefiniteness, but “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103 to show inherency.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
No Information Disclosure Statement
5. No IDS has been filed as of this office action date.
Specification Objections
6a. The Title is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
6b. The disclosure “Background” section does not discuss any meaningful problem to be solved or background information and is objected. See MPEP § 608.01(c).
See 37 C.F.R. 1.71(b) requires, “The specification must set forth the precise invention for which a patent is solicited, in such manner as to distinguish it from other inventions and from what is old.” Applicant is reminded that helpful guidance, as to preparing an application disclosure, is provided in the MPEP under section 608. Notably, MPEP 608.01(c) provides exemplary use of the heading “Background of the Invention”.
Applicant is requested to check other informality, language, spelling, typo issues, informal marks (if applicable) for specification to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard. Further, Applicant is requested to check all claim informality, language issues (e.g. antecedent issues, redundant limitation issues, sinuous functional language issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 112
7. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
8a. Claims 1, 11, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. Such omission is tantamount to omitting essential structural cooperative relationships of elements also. See MPEP § 2172.01. A claim which omits subject matter disclosed to be essential to the invention as described in the specification or in other statements of record may be rejected as failing to claim the subject matter that the inventor or a joint inventor regards as the invention. See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976); In re Venezia, 530 F.2d 956, 189 USPQ 149 (CCPA 1976); and In re Collier, 397 F.2d 1003, 158 USPQ 266 (CCPA 1968). Such essential matter may include missing elements (circuitry components essential for function), steps or necessary structural cooperative relationships of elements described by the applicant(s) as necessary to practice the invention. For example, for In re Mayhew, the Court of Customs and Patent Appeals (CCPA) held that claims were not enabled under 35 U.S.C. § 112 because they omitted a cooling bath and its specific location, which were deemed essential elements based on the specification. The court found that the specification indicated these elements were critical for the invention to function as described, and their omission from the claims rendered them not supported by an enabling disclosure.
Claim 1 recites combination of “…first access mode signal is for instructing access to the N banks…output a first data signal … write the first data signal into a target bank…” and it appears from spec para [0044]-para [0045], and Fig. 2-Fig. 3 disclosure that the data is accessed, read using bank group mode (first access mode). However, due to omitted elements and omitted essential structural cooperative relationships of elements, it is not clear how and in what mode data is written to individual banks (last clause). Missing elements are description of additional modes, mode switching, additional circuitry structures, read-write mechanism/ cycles (if applicable), connections and functional description. Overall arrangement of the apparatus and function (see Fig. 1 disclosure and para [0043]-para [0044] for missing circuitry structure) is unclear and vague without these circuitry components and additional functional description. Similarly, claim 11 recites “…first access mode signal is for instructing access to the N banks.....outputting a first data signal....writing the first data signal into a target bank…” and claim 18 recites “…first access mode signal is for instructing access to the N banks…output a first data signal… write the first data signal into a target bank…”
8b. All dependent claims inclusive of Claims 1-20 are rejected under this category. See art rejection for the interpretation of the art rejected claims.
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
12. Claims 1, 11, and 18 is/are rejected under 35 U.S.C. 103 as being obvious over Kim (US 2021/0407574 A1), in view of Morita et al. (US 2003/0002316 A1).
Regarding independent claim 1, Kim teaches a memory device (para [0040], Fig. 2: 100 “memory device”. See Fig. 1-Fig. 16 for illustrated components and functionality. See Examiner’s Markup of Figure 4A), comprising:
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a memory cell array (Fig. 2: 110 “memory cell array”) comprising M bank groups, each of which comprises N banks, both M and N being integers larger than 1 (Fig. 3B-Fig. 3C in context of para [0055], para [0057]: 4 bank group, 16 banks);
a peripheral circuit (Fig. 2 non-array circuitry) coupled to the memory cell array (Fig. 2: 110) and configured to:
regulate an internal clock signal (in context of Fig. 4A, Fig. 4D: WCK clock ratio WCK2CK is controlled) in response to a first access mode signal (para [0058], para [0005]: “bank group mode”. See also para [0059]-para [0060]) and output a first clock signal (Fig. 4A, Fig. 4D: CK with target tCCD_S), wherein the first clock signal comprises a plurality of first sampling signals spaced from each other (see Fig. 4A, Fig. 4D: CK signals in transition region; see e.g., S_BG0, S_BG1), and
the first access mode signal is for instructing access to the N banks (para [0058]-para [0060]: bank group mode accesses multiple banks);
output a first data signal (data accessed during bank group access method) in response to the first clock signal (Fig. 4A: CK) and a first local data signal (para [0037], Fig. 4A, Fig. 4D: DQ for BG0)
wherein the first local data signal (Fig. 4A, Fig. 4D: DQ) comprises a plurality of first data periods and a plurality of first interval periods alternating with the plurality of first data periods (see Fig. 4A, Fig. 4D: DQ periods and intervals), and
two adjacent ones of the first sampling signals (Fig. 4A: S_BG0, S_BG1) fall respectively in the first data period and the first interval period adjacent to each other (Fig. 4A: S_BG0, S_BG1 fall in BG0 DQ period and the interval).
write the first data signal into a target bank of the (M*N) banks (in context of para [0036], para [0037], para [0107], para [0109], Fig. 11: teaches both reading and writing using bank group mode and individual bank mode. Disclosed method can be employed to write data to individual bank using “individual bank mode”).
Kim does not explicitly teach accessing/ reading data from a bank group and writing data into a single target bank within a single method.
Morita Fig. 8, para [0087], para [0309], para [0316]-para [0318] teach reading data from bank group (group by GIO lines) and teach writing data to specific individual bank address with a single method. See Morita Fig. 8.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Morita into the teachings of Kim such that Morita’s data bus structure and data latch/ transmission method can be employed in Kim’s apparatus to implement read-write method in order to avoid data collision, improve operational speed.
Regarding independent claim 11, Kim and Morita teach an operation method of a memory device, wherein the memory device comprises a memory cell array comprising M bank groups, each of which comprises N banks, both M and N are integers larger than 1, and the operation method comprises: regulating an internal clock signal in response to a first access mode signal and outputting a first clock signal, wherein the first clock signal comprises a plurality of first sampling signals spaced from each other, and the first access mode signal is for instructing access to the N banks; outputting a first data signal in response to the first clock signal and a first local data signal, wherein the first local data signal comprises a plurality of first data periods and a plurality of first interval periods alternating with the plurality of first data periods, and two adjacent ones of the first sampling signals fall respectively in the first data period and the first interval period adjacent to each other; and writing the first data signal into a target bank of the (M*N) banks.
(This claim is drafted as in method format, substantially identical to the functionality recited in claim 1, and is therefore rejected for the same reasons as claim 1. See claim 1 rejection analysis)
Regarding independent claim 18, Kim and Morita teach a memory system, comprising: a memory device, comprising: a memory cell array comprising M bank groups, each of which comprises N banks, both M and N being integers larger than 1; a peripheral circuit coupled to the memory cell array and configured to: regulate an internal clock signal in response to a first access mode signal and output a first clock signal, wherein the first clock signal comprises a plurality of first sampling signals spaced from each other, and the first access mode signal is for instructing access to the N banks; output a first data signal in response to the first clock signal and a first local data signal, wherein the first local data signal comprises a plurality of first data periods and a plurality of first interval periods alternating with the plurality of first data periods, and two adjacent ones of the first sampling signals fall respectively in the first data period and the first interval period adjacent to each other; and write the first data signal into a target bank of the (M*N) banks; and a memory controller coupled to the memory device and configured to control the memory device.
(This claim is drafted as in system claim format, substantially identical to the functionality recited in claim 1, and is therefore rejected for the same reasons as claim 1. See claim 1 rejection analysis)
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure : Tomishima (US 2016/0378366 A1): Fig. 1-Fig. 8 disclosure applicable for all claims. KIM-2924 (US 2011/0242924 A1) is applicable: KIM-2924 teaches a semiconductor device (Fig. 1: 10 “semiconductor memory device”. See Fig. 1-Fig. 11 for components and functionality) comprising: a bank group control circuit (Fig. 1: 100, 200, 400 combined) configured to generate a bank group enablement signal (combination of signals MCS1, MCS2. See para [0048]: enables “Group mode” and “non-group mode”), a first column control signal (Fig. 10: CSL1. See para [0050]: first column decoder 432 signal), and a second column control signal (Fig. 10: CSL2. See para [0050]: second column decoder 434 signal) based on an internal command/address signal (para [0045]: command, address signals) that is inputted while an internal chip selection signal has a first logic level (para [0045]: “chip select signal”. Chip select is enabled to sample command, address from controller); and a bank group (e.g. Fig. 9: GPA. See also Fig. 4-Fig. 6 bank group arrangement which is configurable) configured to include first to fourth banks (Fig. 9: see e.g. 1G configuration: BANK 0-3: GPA. See para [0071]), wherein the bank group includes a common circuit (e.g. Fig. 2, 5: 432, 431 decoders) to perform a column operation for at least two of the first to fourth banks (Fig. 10: GPA banks e.g. 4 banks are read) based on the bank group enablement signal (combination of signals MCS1, MCS2 indicating “group mode”) and the first and second column control signals (Fig. 10: 520 portion. Fig. 10 in context of Para [0074]: GPA is read using CSL1, CSL2). KIM (US 2017/0109308 A1): Fig. 1-Fig. 17B disclosure applicable for all claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached on 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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