Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/27/25 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,224,482. Although the claims at issue are not identical, they are not patentably distinct from each other because both sets of claims recites he same subject matter with colorable differences.
Claim 1 of the present application recites:
A three-dimensional (3D) integrated circuit (IC) package, comprising: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a through-substrate via (TSV) through the first substrate and electrically connecting the first IC die and the second IC die, the TSV comprising a TSV cell having a TSV cell boundary a keep-out zone (KOZ) surrounding the TSV; and at least one diode a protection module fabricated in the first substrate, wherein the at least one diode is electrically connected to the TSV, wherein the protection module at least one diode is fabricated within the KOZ TSV cell boundary surrounding the TSV, and wherein no functional cell is fabricated within the KOZ TSV cell boundary.
Claim 1 recites the same limitation as claim 1 of the patent except for the limitation of a keep out zone (KOZ) which is recited in claim 5 of the patent that depends on claim 1.
Claim 2 of the present application recites:
2. The 3D IC package of claim 1, wherein the protection module is an antenna protection module configured to provide antenna effect protection to the first IC die.
This claim is identical to the limitations of claim 2 of the patent.
Claim 3 of the present application recites:
3. The 3D IC package of claim 2, wherein antenna protection module is an antenna diode. Diode is a electronic device known to protect sensitive equipment.
Claim 4 of the present application recites:
The 3D IC package of claim 1, wherein the protection module is an electrostatic discharge (ESD) protection module configured to provide ESD protection to the first IC die. ESD also called diode as often Transient Voltage Suppression diodes is known to protect electronic equipment.
Claim 5 of the present application recites:
The 3D IC package of claim 4, wherein the ESD protection module includes multiple diodes connected in parallel.
This claim is identical to the limitations of claim 3 of the patent.
Claim 6 of the present application recites:
The 3D IC package of claim 4, wherein the ESD protection module is one of: a bipolar transistor, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a silicon-controlled rectifier (SCR).
This claim is identical to the limitations of claim 4 of the patent.
Claim 7 of the present application recites:
The 3D IC package of claim 1, wherein the protection module is outside a TSV buffer zone of the TSV.
This claim is identical to the limitations of claim 6 of the patent.
Claim 8 of the present application recites:
The 3D IC package of claim 1, wherein the KOZ has a plurality of rows, and the protection module is placed on one of the plurality of rows.
This claim is identical to the limitations of claim 7 of the patent.
Claim 9 of the patent recites:
The 3D IC package of claim 1, wherein the first IC die comprises a transistor in a functional cell, the transistor having an enlarged gate polysilicon area.
This claim is identical to the limitations of claim 8 of the patent.
Claim 10 of the patent recites:
A three-dimensional (3D) integrated circuit (IC) package, comprising: a first IC die comprising a first substrate at a back side of the first IC die;
a second IC die stacked at the back front side of the first IC die and facing the first substrate;
a hybrid bonding (HB) structure bonding the first IC die and the second IC die, the HB structure having a HB region surrounding the HB structure;
and a transistor at least one diode fabricated in the first substrate, wherein the transistor at least one diode is electrically connected to the HB structure, the transistor at least one diode is fabricated within the HB region surrounding the HB structure, and wherein no functional cell is fabricated within the HB region.
This claim is quasi-identical to the limitations of claim 9 of the patent.
Claim 11 of the patent recites:
The 3D IC package of claim 10, wherein the at least one diode is configured to provide antenna effect protection to the first IC die.
This claim is identical to the limitations of claim 10 of the patent.
Claim 12 of the patent recites
The 3D IC package of claim 10, wherein the at least one diode comprises multiple diodes connected in parallel.
This claim is identical to the limitations of claim 11 of the patent.
Claim 13 of the patent recites:
The 3D IC package of claim 10, wherein the at least one diode is electrically connected to the HB structure through a multi-layer interconnect (MLI) structure.
This claim is identical to the limitations of claim 12 of the patent.
Claim 14 of the patent recites:
The 3D IC package of claim 13, wherein the HB structure comprises a HB metal layer and a HB contact structure, the HB contact structure electrically connecting the HB metal layer and the MLI structure.
This claim is identical to the limitations of claim 13 of the patent.
Claim 15 of the patent recites:
15. A method, comprising: providing a first IC die comprising a first substrate at a back side of the first IC die; fabricating a through-substrate via (TSV) through the first substrate, the TSV comprising a TSV cell having a TSV cell boundary TSV a keep-out zone (KOZ) surrounding the TSV; fabricating a protection module in the first substrate, wherein the protection module is electrically connected to the TSV, wherein the protection module is within the KOZ TSV cell boundary surrounding the TSV, and wherein no functional cell is fabricated within the KOZ TSV cell boundary; providing a second IC die at a front back side of the first IC die; and
bonding the second IC die to the first IC die, the first IC die and the second IC die being electrically connected through the TSV.
This claim is quasi-identical to the limitations of claim 15 of the patent.
Claim 16 of the patent recites:
16. The method of claim 15, wherein the ESD protection module is one of: an antenna protection module configured to provide antenna effect protection to the first IC die.
This claim is identical to the limitations of claim 16 of the patent.
Claim 17 of the patent recites:
17. The method of claim 15, wherein the ESD protection module comprises one of the following: a diode, a bipolar transistor, a metal-oxide-semiconductor field- effect transistor (MOSFET), and a silicon-controlled rectifier (SCR).
This claim is identical to the limitations of claim 17 of the patent.
Claim 18 of the patent recites:
The method of claim 15, wherein the ESD protection module comprises a plurality of diodes connected in parallel.
This claim is identical to the limitations of claim 13 of the patent.
Claim 19 of the patent recites:
19. The method of claim 15, wherein the ESD protection module is outside a TSV buffer zone of the TSV.
This claim is identical to the limitations of claim 19 of the patent.
Claim 20 of the patent recites:
20. The method package of claim 15, wherein the TSV cell has KOZ comprises a plurality of rows, and the ESD protection module is placed on one of the plurality of rows.
This claim is identical to the limitations of claim 20 of the patent.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105.
/PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845
Prosecution Insights