Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
35 U.S.C. 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-4 and 18-19 are rejected under 35 U.S.C. 103(a) as being unpatentable over (HASSNER – KR 20220063390 A) in view of (SONG – KR 20240012254 A).
With respect to claim 1, the HASSNER reference teaches At least one core die, configured to provide at least two state signals based on error check and correction (ECC) operation (page 7, lines 20-34 - Row control circuitry 520 receives M row address signals and a group of one or more various control signals from system control logic circuitry 560 and typically includes a row decoder 522 for both read and write operations).
The HASSNER reference does not teach and a logic die, coupled to the least one core die, and configured to generate the at least two state signals to generate a plurality of severity signals, wherein a number of the at least two state signals is lower than a number of the plurality of severity signals.
The SONG reference teaches and a logic die, coupled to the least one core die, and configured to generate the at least two state signals to generate a plurality of severity signals, wherein a number of the at least two state signals is lower than a number of the plurality of severity signals (page 12, lines 20 – 36 - perform ECC decoding based on the test parity data (TPRT) stored in the second latch 427, generate a severity signal (SEV2) based on the result of ECC decoding, and transmit the severity signal (SEV2) to the memory controller 100. ).
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references HASSNER and SONG to incorporate and a logic die, coupled to the least one core die, and configured to generate the at least two state signals to generate a plurality of severity signals, wherein a number of the at least two state signals is lower than a number of the plurality of severity signals into the claimed invention.
The motivation for and a logic die, coupled to the least one core die, and configured to generate the at least two state signals to generate a plurality of severity signals, wherein a number of the at least two state signals is lower than a number of the plurality of severity signals is improving testing (page 2, lines 56-57 - SONG).
With respect to claims 2, the HASSNER reference teaches wherein the logic die comprises: a pre-encoder, coupled to the least one core die, and configured to generate a first error output signal and a second error output signal according to the at least two state signals (page 32, line 11-19 – Even if there is one or more bits of error within the data, the ECC engine 569 may report that the decoding passed, which is referred to herein as a miscorrection or undetectable error.).
The HASSNER reference does not teach and a severity signal generator, coupled to the pre-encoder, and configured to generate a plurality of severity signals according to the first error output signal and the second error output signal.
The SONG reference and a severity signal generator, coupled to the pre-encoder, and configured to generate a plurality of severity signals according to the first error output signal and the second error output signal ((page 12, lines 20 – 36 - perform ECC decoding based on the test parity data (TPRT) stored in the second latch 427, generate a severity signal (SEV2) based on the result of ECC decoding, and transmit the severity signal (SEV2) to the memory controller 100. ).
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references HASSNER and SONG to incorporate and a severity signal generator, coupled to the pre-encoder, and configured to generate a plurality of severity signals according to the first error output signal and the second error output signal into the claimed invention.
The motivation for and a severity signal generator, coupled to the pre-encoder, and configured to generate a plurality of severity signals according to the first error output signal and the second error output signal is for improving testing (page 2, lines 56-57 - SONG).
With respect to claims 3, all of the limitations of claim 2 have been addressed.
The HASSNER reference does not teach wherein the logic die further comprising: a serializer, coupled to the severity signal generator, and configured to generate at least one serial severity signal according to the plurality of severity signal.
The SONG reference wherein the logic die further comprising: a serializer, coupled to the severity signal generator, and configured to generate at least one serial severity signal according to the plurality of severity signal (page 13, line 50 – 53 - generates a severity signal (CE) indicating that one error bit has been corrected (CE)).
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references HASSNER and SONG to incorporate wherein the logic die further comprising: a serializer, coupled to the severity signal generator, and configured to generate at least one serial severity signal according to the plurality of severity signal into the claimed invention.
The motivation for wherein the logic die further comprising: a serializer, coupled to the severity signal generator, and configured to generate at least one serial severity signal according to the plurality of severity signal is for reliability is for improving testing (page 2, lines 56-57 - SONG).
With respect to claims 4, all of the limitations of claim 3 have been addressed.
The HASSNER reference does not teach a controller, coupled to the serializer, and configured to obtain an error type of the least one core die according to the at least one serial severity signal.
The SONG reference a controller, coupled to the serializer, and configured to obtain an error type of the least one core die according to the at least one serial severity signal (page 26, line 35 – 40 - the error pattern output (Error Pattern Output) may correspond to the corrected test data (C_TD) of FIG. 16. , Parity Error may correspond to the test parity data (TPRT) of FIG. 16, the severity signal result (SEV Result) may correspond to the severity signal (SEV) of FIG. 16, and the expected severity signal (Expected) SEV) may be a severity signal that the CPU 110 of FIG. 2 predicts for various error patterns).
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references HASSNER and SONG to incorporate a controller, coupled to the serializer, and configured to obtain an error type of the least one core die according to the at least one serial severity signal into the claimed invention.
The motivation for a controller, coupled to the serializer, and configured to obtain an error type of the least one core die according to the at least one serial severity signal.
is for improving testing (page 2, lines 56-57 - SONG).
With respect to claim 18, all of the limitations of claim 2 have been addressed.
The HASSNER reference does not teach wherein: the plurality of severity signals are grouped into a first signal group and a second signal group, and the severity signal generator provides the first signal group having a first logic value, and provides the second signal group according to the first error output signal and the second error output signal..
The SONG reference wherein: the plurality of severity signals are grouped into a first signal group and a second signal group, and the severity signal generator provides the first signal group having a first logic value, and provides the second signal group according to the first error output signal and the second error output signal. (page 12, lines 20 – 36 - perform ECC decoding based on the test parity data (TPRT) stored in the second latch 427, generate a severity signal (SEV2) based on the result of ECC decoding, and transmit the severity signal (SEV2) to the memory controller 100. ).
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references HASSNER and SONG to incorporate wherein: the plurality of severity signals are grouped into a first signal group and a second signal group, and the severity signal generator provides the first signal group having a first logic value, and provides the second signal group according to the first error output signal and the second error output signal into the claimed invention.
The motivation for wherein: the plurality of severity signals are grouped into a first signal group and a second signal group, and the severity signal generator provides the first signal group having a first logic value, and provides the second signal group according to the first error output signal and the second error output signal. is for improving testing (page 2, lines 56-57 - SONG).
With respect to claim 19, the HASSNER reference teaches wherein the least one core die comprises: an ECC circuit, configured to perform the ECC operation of the least one core die to generate the at least two state signals (page 12, lines 20 – 36 - perform ECC decoding based on the test parity data (TPRT) stored in the second latch 427, generate a severity signal (SEV2) based on the result of ECC decoding, and transmit the severity signal (SEV2) to the memory controller 100. ).
Allowability
Claim 5-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Enam Ahmed whose telephone number is 571-270-1729. The examiner can normally be reached on Mon-Fri from 8:30 A.M. to 5:30 P.M. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert Decady, can be reached on 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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EA
8/16/26
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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