DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo et. al. [11,177,337].
Regarding claim 1, Seo teaches:
A display device comprising: sub-pixel circuits disposed on a substrate and arranged in a first direction and a second direction intersecting the first direction [fig. 4, note unit P];
a horizontal panel constant voltage line disposed on the substrate, extending in the first direction, and transmitting a panel constant voltage to the sub-pixel circuits [fig. 4, Vint line];
vertical panel constant voltage line disposed on the horizontal panel constant voltage line, extending in the second direction, and transmitting the panel constant voltage to the horizontal panel constant voltage line [fig. 4, note PL line];
and a vertical bypass data line disposed on a same layer as the vertical panel constant voltage line, extending in the second direction, and transmitting a data voltage to the sub-pixel circuits [fig. 7, note line J, also note col. 13, lines 41-61, wherein bypass lines J and constant voltage vertical lines PL are on the same layer, as seen from the top of the display device].
Regarding claim 2, Seo further teaches:
wherein the vertical panel constant voltage line is disconnected from the vertical bypass data line [fig. 7, note line J, also note col. 13, lines 41-61, wherein bypass lines J and constant voltage vertical lines PL are on the same layer, as seen from the top of the display device, but are not directly in contact with each other].
Regarding claim 20, Seo further teaches:
An electronic device comprising: a display device [fig. 4, note pixels for digital display P];
and a power supply configured to provide power to the display device [col. 9, lines 34-53, note power supply from controller unit],
wherein the display device comprises: sub-pixel circuits disposed on a substrate and arranged in a first direction and a second direction intersecting the first direction [fig. 4, note unit P];
a horizontal panel constant voltage line disposed on the substrate, extending in the first direction, and transmitting a panel constant voltage to the sub-pixel circuits [fig. 4, Vint line];
vertical panel constant voltage line disposed on the horizontal panel constant voltage line, extending in the second direction, and transmitting the panel constant voltage to the horizontal panel constant voltage line [fig. 4, note PL line];
and a vertical bypass data line disposed on a same layer as the vertical panel constant voltage line, extending in the second direction, and transmitting a data voltage to the sub-pixel circuits [fig. 7, note line J, also note col. 13, lines 41-61, wherein bypass lines J and constant voltage vertical lines PL are on the same layer, as seen from the top of the display device].
Allowable Subject Matter
Claims 3-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 3-19, the prior art of record does not teach “…a panel constant connecting pattern disposed between the horizontal panel constant voltage line and the vertical panel constant voltage line, and electrically connecting the horizontal panel constant voltage line and the vertical panel constant voltage line” when also included with the language of parent claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Lee et. al. [11,854,485], Bei et. al. [2019/0051670], Tanaka et. al. [9,685,131] and Lee et. al. [2016/0055794].
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/ANDREW SASINOWSKI/Primary Examiner, Art Unit 2625