Office Action Predictor
Last updated: April 16, 2026
Application No. 19/050,116

DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME

Non-Final OA §102
Filed
Feb 11, 2025
Examiner
SASINOWSKI, ANDREW
Art Unit
2625
Tech Center
2600 — Communications
Assignee
Samsung Display Co., LTD.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
92%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
664 granted / 855 resolved
+15.7% vs TC avg
Moderate +14% lift
Without
With
+14.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
9 currently pending
Career history
864
Total Applications
across all art units

Statute-Specific Performance

§101
4.0%
-36.0% vs TC avg
§103
43.6%
+3.6% vs TC avg
§102
35.7%
-4.3% vs TC avg
§112
9.8%
-30.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 855 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo et. al. [11,177,337]. Regarding claim 1, Seo teaches: A display device comprising: sub-pixel circuits disposed on a substrate and arranged in a first direction and a second direction intersecting the first direction [fig. 4, note unit P]; a horizontal panel constant voltage line disposed on the substrate, extending in the first direction, and transmitting a panel constant voltage to the sub-pixel circuits [fig. 4, Vint line]; vertical panel constant voltage line disposed on the horizontal panel constant voltage line, extending in the second direction, and transmitting the panel constant voltage to the horizontal panel constant voltage line [fig. 4, note PL line]; and a vertical bypass data line disposed on a same layer as the vertical panel constant voltage line, extending in the second direction, and transmitting a data voltage to the sub-pixel circuits [fig. 7, note line J, also note col. 13, lines 41-61, wherein bypass lines J and constant voltage vertical lines PL are on the same layer, as seen from the top of the display device]. Regarding claim 2, Seo further teaches: wherein the vertical panel constant voltage line is disconnected from the vertical bypass data line [fig. 7, note line J, also note col. 13, lines 41-61, wherein bypass lines J and constant voltage vertical lines PL are on the same layer, as seen from the top of the display device, but are not directly in contact with each other]. Regarding claim 20, Seo further teaches: An electronic device comprising: a display device [fig. 4, note pixels for digital display P]; and a power supply configured to provide power to the display device [col. 9, lines 34-53, note power supply from controller unit], wherein the display device comprises: sub-pixel circuits disposed on a substrate and arranged in a first direction and a second direction intersecting the first direction [fig. 4, note unit P]; a horizontal panel constant voltage line disposed on the substrate, extending in the first direction, and transmitting a panel constant voltage to the sub-pixel circuits [fig. 4, Vint line]; vertical panel constant voltage line disposed on the horizontal panel constant voltage line, extending in the second direction, and transmitting the panel constant voltage to the horizontal panel constant voltage line [fig. 4, note PL line]; and a vertical bypass data line disposed on a same layer as the vertical panel constant voltage line, extending in the second direction, and transmitting a data voltage to the sub-pixel circuits [fig. 7, note line J, also note col. 13, lines 41-61, wherein bypass lines J and constant voltage vertical lines PL are on the same layer, as seen from the top of the display device]. Allowable Subject Matter Claims 3-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claims 3-19, the prior art of record does not teach “…a panel constant connecting pattern disposed between the horizontal panel constant voltage line and the vertical panel constant voltage line, and electrically connecting the horizontal panel constant voltage line and the vertical panel constant voltage line” when also included with the language of parent claim 1. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Lee et. al. [11,854,485], Bei et. al. [2019/0051670], Tanaka et. al. [9,685,131] and Lee et. al. [2016/0055794]. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW SASINOWSKI whose telephone number is (571)270-5883. The examiner can normally be reached 7am - 4pm, Mon.-Fri. EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached at 571-272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANDREW SASINOWSKI/Primary Examiner, Art Unit 2625
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Prosecution Timeline

Feb 11, 2025
Application Filed
Dec 08, 2025
Non-Final Rejection — §102
Mar 27, 2026
Response Filed

Precedent Cases

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2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
92%
With Interview (+14.1%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 855 resolved cases by this examiner. Grant probability derived from career allow rate.

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