DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 11 and 12 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Cho et al. (US Pat Pub 2023/0143829).
Regarding claims 1 and 12, Cho et al. disclose a memory device (figs. 1 – 25 and all related texts), comprising:
a plurality of page buffers (for example the page buffers PBU0 – PBUn, fig. 5), wherein the plurality of page buffers are coupled in series (as shown in 210 of fig. 5); and
a plurality of first switches (TR0/TR0’, TR1/TR1’, TR2/TR2’, TR3/TR3’, etc…, fig. 12 for example), respectively corresponding to the plurality of page buffers (switches as part of the page buffers PBU1-PBU3, etc…, fig. 12 and other figs.),
wherein each of the plurality of first switches is coupled to a sensing node of the corresponding page buffer (para 0040, sensingnode MT0a electrically connecting the pair of passing transistor to each other),
wherein each of the plurality of first switches receives a reference voltage (referred to in para 0087 as first pass control signal SO_PASS0 – SO_PASS3, etc…, fig. 12), and provides a source current to the sensing node of the corresponding page buffer (see abstract, para 0005, 0006, 0008, 0040, etc…) after a data sensing period (see para 0008, 0040, 0150, 0112, etc…).
Regarding claim 11, Cho et al. also disclose the memory device according to claim 1, wherein each of the plurality of first switches is a transistor switch (as shown in fig. 12, the switches are made up of transistors TR0-TR3, etc…).
Allowable Subject Matter
Claims 2 – 10 and 13 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record fail to teach or reasonably suggest the memory device & operation method for the memory device as set forth above, further comprising, in combination, the features and limitations additionally claimed at least in claims 2, 3, 5 – 7, 13, 14, and 16 – 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See additional cited references for related disclosures to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
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LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 July 20, 2026
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