DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 16, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bhowmik et al. (US 7,675,333).
Regarding claim 1, Bhowmik et al. (Fig. 1) discloses a delay circuit (100), comprising:
a delay chain (105) comprising a plurality of delay cells (P) coupled in series, wherein the delay chain provides a delay amount, and delays a clock signal by the delay amount to generate a delayed clock signal (Fig. 2; col. 3, lines 50-65); and
a calibration circuit (110/120; Fig. 3) coupled to the delay chain (105), counting a number of pulses of the delayed clock signal during a preset time period to generate a count value (Fig. 4; “…the masking module 140 include, but not limited to digital counters. The first mask module 145 masks edges of the REFCLK and the second mask module 150 masks the DELCLK edges…”), and generating calibration information according to the count value (col. 4, lines 9-67);
wherein the delay chain (105) adjusts the delay amount (by the phase control signal as illustrated in Fig. 1) by adjusting a transmission delay of at least one of the delay cells according to the calibration information (col. 5, lines 22-25).
Regarding claim 5, Bhowmik et al. (Fig. 1) discloses the delay circuit (105) as claimed in claim 1, wherein the delay cells (P) respectively comprise a plurality of signal buffers (Fig. 2), and at least one of the delay cells is a selected delay cell, wherein the selected delay cell adjusts the transmission delay according to the calibration information (col. 5, lines 22-40).
Regarding claim 16, Bhowmik et al. (Fig. 1) discloses a delay amount controlling method, comprising:
providing a delay amount by a delay chain (105), wherein the delay chain has a plurality of delay cells coupled in series (Fig. 2);
generating a delayed clock signal (DELCLK) by delaying a clock signal according to the delay amount (Fig. 2; col. 3, lines 50-65);
counting a number of pulses of the delayed clock signal to generate a count value during a preset time period (Fig. 4; “…the masking module 140 include, but not limited to digital counters. The first mask module 145 masks edges of the REFCLK and the second mask module 150 masks the DELCLK edges…”);
generating calibration information according to the count value (col. 4, lines 9-67); and
adjusting (by the phase control signal as illustrated in Fig. 1) the delay amount by adjusting a transmission delay of at least one of the delay cells according to the calibration information (col. 5, lines 22-25).
Regarding claim 18, Bhowmik et al. (Fig. 1) discloses the delay amount controlling method as claimed in claim 16, further comprising: decreasing the delay amount (adjusting by the phase control signal shown in Fig. 2) in response to the calibration information increasing (col. 5, lines 22-25).
Allowable Subject Matter
Claims 8-15 are allowed.
Claims 2-4, 6-7 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 2-4, Bhowmik et al. is not seen to disclose or suggest the calibration circuit that includes: “…a comparator coupled to the counter, comparing the count value with a threshold to generate the calibration information”.
Regarding claim 6, Bhowmik et al. is not seen to disclose or suggest “the selected delay cell comprises: a current source coupled in a path where a corresponding one of the signal buffers receives a reference ground voltage, wherein the current source provides a sink current according to the calibration information”.
Regarding claim 7, Bhowmik et al. is not seen to disclose or suggest “the selected delay cell comprises: a current source coupled in a path where a corresponding one of the signal buffers receives a power supply voltage, wherein the current source provides a source current according to the calibration information”.
Regarding claims 8-15, Bhowmik et al. is not seen to disclose or suggest “the comparison circuit [710] for comparing a sampling voltage with a reference voltage based on a clock signal to generate a comparison ready signal [CK_ready]; and a controller [720] comprising a delay circuit [721] and a logic circuit [722], wherein the logic circuit determines whether a metastable event occurs according to the comparison ready signal, and the delay circuit provides a delayed clock signal, wherein the delay circuit comprises: a delay chain comprising a plurality of delay cells coupled in series…”.
Regarding claim 17, Bhowmik et al. is not seen to disclose or suggest the step of “increasing the calibration information by an offset value in response to the count value being less than a threshold”.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
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/KHAI M NGUYEN/Primary Examiner, Art Unit 2845
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