DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' application filed on 02/11/25. Claims 1-20 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 14-16, 19-20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gurcan et al. (US 20080174289 A1)
Regarding claim 1. Gurcan teaches a voltage regulator circuit [fig 2], comprising: an input stage [102], configured to compare a reference voltage and a feedback voltage to generate a first voltage [VINT] at a first output terminal [128] of the input stage;
a transconductance compensation stage [104, ¶39-¶40], coupled between [104 is between input terminal of 102 and output terminal of 102] the first output terminal and an internal node [118 of 102] of the input stage, and configured to change an overall transconductance of the input stage in response to a change in the feedback voltage;
a driving stage [106], coupled between the first output terminal and a second output terminal [vout] of the voltage regulator circuit, and configured to provide a driving current to the second output terminal which is coupled to a load [RL];
and a feedback circuit [see 150 excluding RL], coupled to the second output terminal, and configured to generate the feedback voltage based on an output voltage of the voltage regulator circuit.
Regarding claim 2. Gurcan teaches the voltage regulator circuit of Claim 1, wherein the input stage is implemented using a differential amplifier [i.e. see 102], an operational amplifier, or an operational transconductance amplifier.
Regarding claim 3. Gurcan teaches the voltage regulator circuit of Claim 2, wherein the transconductance compensation stage is further configured to generate a compensation current [308/310] based on the first voltage generated by the input stage, and provide the compensation current to the input stage in addition [bias signals from 118 is viewed as negative addition] to a bias current of the input stage [¶40].
Regarding claim 4. Gurcan teaches the voltage regulator circuit of Claim 3, wherein the driving current is divided into a load current [IL] flowing into the load and a feedback current [current of 112] flowing through the feedback circuit.
Regarding claim 5. Gurcan teaches the voltage regulator circuit of Claim 4, wherein the feedback circuit is implemented using a voltage divider with a feedback factor, and the feedback voltage is obtained by multiplying the output voltage with the feedback factor [see feedback circuit of 150].
Regarding claim 6. Gurcan teaches the voltage regulator circuit of Claim 5, wherein the input stage comprises a first input terminal receiving the reference voltage [126] and a second input terminal receiving the feedback voltage [- terminal], and the input stage is biased by the bias current plus the compensation current [VINT is bias by 118].
Regarding claim 7. Gurcan teaches the voltage regulator circuit of Claim 6, wherein the transconductance compensation stage comprises: a first stage [302/304], coupled to the first output terminal, and biased by the bias current [i.e. 118]; and a second stage [312/314], coupled to the first stage, and configured to generate the compensation current based on a second voltage generated by the first stage [¶40].
Regarding claim 8. Gurcan teaches the voltage regulator circuit of Claim 7, wherein the driving stage is further configured to generate the driving current based on the second voltage generated by the first stage [function of 106].
Regarding claim 14. Gurcan teaches a voltage regulator circuit [fig 2], comprising: an input stage [102], configured to compare a reference voltage and a feedback voltage to generate a first voltage [VINT] at a first output terminal [128] of the input stage; a dynamic frequency compensation stage [104, ¶39-¶40, by virtue of its capacity to alter the loop gain, pole locations as operating conditions vary], coupled between the first output terminal and an internal node of the input stage, and configured to perform a dynamic frequency compensation based on the feedback voltage to increase a unity-gain frequency [increasing the transconductance increases the unity gain] of the voltage regulator circuit in response to a change in a load current of a load [RL] coupled to a second output terminal [vout] of the voltage regulator circuit, wherein the dynamic frequency compensation stage includes at least one transistor [any transistor of fig 4]; a driving stage [106], coupled between the first output terminal and the second output terminal, and configured to provide a driving current to the second output terminal;
and a feedback circuit [see 150 excluding RL], coupled to the second output terminal, and configured to generate the feedback voltage based on an output voltage of the voltage regulator circuit.
Regarding claim 15. Gurcan teaches the voltage regulator circuit of Claim 14, wherein dynamic frequency compensation stage does not include a capacitor [fig 4, lacks a capacitor].
Regarding claim 16. Gurcan teaches the voltage regulator circuit of Claim 14, wherein the feedback circuit is implemented using a voltage divider [see 150] with a feedback factor, and the feedback voltage is obtained by multiplying the output voltage with the feedback factor.
Regarding method claims 19-20, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device "inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Allowable Subject Matter
Claims 9-13, 17-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838
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