DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 contains the language “about 0V.” This language is hereby deemed to be indefinite since it is not clear which voltage value would be understood by a person of ordinary skill in the art to be “about zero.” Please refer to MPEP 2173.05(b) III A. “About.”
In determining the range encompassed by the term "about," one must consider the context of the term as it is used in the specification and claims of the application. Ortho-McNeil Pharm., Inc. v. Caraco Pharm. Labs., Ltd., 476 F.3d 1321, 1326, 81 USPQ2d 1427, 1432 (Fed. Cir. 2007). In W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), the court held that a limitation defining the stretch rate of a plastic as "exceeding about 10% per second" is definite because infringement could clearly be assessed through the use of a stopwatch. However, in another case, the court held that claims reciting "at least about" were invalid for indefiniteness where there was close prior art and there was nothing in the specification, prosecution history, or the prior art to provide any indication as to what range of specific activity is covered by the term "about." Amgen, Inc. v. Chugai Pharmaceutical Co., 927 F.2d 1200, 18 USPQ2d 1016 (Fed. Cir. 1991).
The language of “about 0V” does not indicate what range of specific values are covered by such language.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Watakabe et al (Publication number: US 2023/0169922) in view Puckett et al (Publication number: US 2020/0106421).
Consider Claim 1, Watakabe et al shows a method for inspecting a display panel (see the pixel circuit of figure 18), the method comprising:
(a) In a pixel comprising a light emitting element and a first transistor connected to the light emitting element, applying a first voltage to a first electrode of the first transistor (see figures 18 and 19; and paragraphs 134, and 137); (The light emitting element is read as the OLED, the first transistor is read as driving transistor DRT, the first voltage is read as PVDD).
(b) Applying a second voltage having a lower level than the first voltage to a second electrode of the first transistor (see figure 18); (The second voltage is read as PVSS).
(c) Measuring a current flowing through the first transistor via a data line connected to the first electrode of the first transistor, wherein an initial level of the control voltage is the same as the level of the first voltage (see figure 14; and paragraphs 154-158); (In order to determine degradation of driving transistor 310, a current passing through the transistor is measured).
However, Watakabe et al does not specifically show applying a control voltage to a control electrode of the first transistor; and gradually varying a level of the control voltage such that the level of the control voltage is lowered.
Puckett et al shows applying a control voltage to a control electrode of the first transistor; and gradually varying a level of the control voltage such that the level of the control voltage is lowered (see paragraphs 21 and 22); (If the high voltage is received for a long duration, the balancing transistor may, by increasing the voltage at the source of the inverter pair NMOS, decrease the gate-source voltage differential associated with the inverter pair NMOS. In this manner, BTI degradation of the inverter pair NMOS due to a sustained high voltage may be prevented).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the voltage decreasing mechanism of Puckett et al into the pixel circuit of Watanabe et al in order to prevent degradation due to a sustained high voltage (see Puckett et al; paragraphs 21 and 22).
Consider Claim 2, Puckett et al shows varying of the level of the control voltage comprises gradually decreasing the level of the control voltage to a first level that is lower than the initial level (see paragraphs 21 and 22); (If the high voltage is received for a long duration, the balancing transistor may, by increasing the voltage at the source of the inverter pair NMOS, decrease the gate-source voltage differential associated with the inverter pair NMOS. In this manner, BTI degradation of the inverter pair NMOS due to a sustained high voltage may be prevented).
Consider Claim 3, Puckett et al show that the first transistor is turned off based on an absolute value of the control voltage being smaller than an absolute value of the first level (see paragraphs 40 and 41).
Consider Claim 5, Puckett et al shows varying of the level of the control voltage further comprises gradually decreasing the level of the control voltage to a second level that is lower than the first level (see paragraphs 21 and 22); (If the high voltage is received for a long duration, the balancing transistor may, by increasing the voltage at the source of the inverter pair NMOS, decrease the gate-source voltage differential associated with the inverter pair NMOS. In this manner, BTI degradation of the inverter pair NMOS due to a sustained high voltage may be prevented).
Consider Claim 11, Watakabe et al show that the initial level is about 0V (see figures 17, 23, and 24).
Consider Claim 13, Puckett et al shows that the first transistor is a PMOS transistor (see paragraphs 20-22).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Watakabe et al (Publication number: US 2023/0169922) in view Puckett et al (Publication number: US 2020/0106421) in view of Toyomura (Publication number: US 2022/0383815).
Consider Claim 12, Watakabe et al in view of Puckett et al do not specifically show that the second voltage is set to a negative voltage.
In related art, Toyomura shows that the second voltage is set to a negative voltage (see paragraphs 126-128).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Toyomura into the teaching of Watakabe and Puckett in order to accommodate p-channel drive transistors (see Toyomura; paragraphs 126-128).
Allowable Subject Matter
Claims 18-20 are allowed.
Claims 4, 6-10, and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
An allowability agreement seems to be possible in view of claims 1-3, 5, and 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A FARAGALLA whose telephone number is (571)270-1107. The examiner can normally be reached Mon-Fri 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 01/07/2026