DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 02/13/2025. Claims 1-21 are pending in the Application, of which Claims 1, 8 and 15 are independent.
Continuity/ Priority Information
The present Application 19052307 filed 02/13/2025 claims foreign priority to TAIWAN Application 114100202, filed 01/03/2025.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/20/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHU et al. (Pub. No. US 20180336960) Pub. Date: 2018-11-22.
Regarding independent Claims 1, 8 and 15, CHU discloses detection of die failure in flash memory devices, comprising:
setting a timer after powering on, wherein the timer corresponds to a first physical unit among the physical units;
[0031] At time t.sub.0 250, the controller 120 may detect that a program operation is being performed “setting a timer”. In an example, this could be determined by tracking that a program command has been issued by the controller 120. [0032] A time interval 240 (“tPROG”) represents a period of time for programming data on the flash memory device 130, and in particular with respect to programming data on one of the flash memory dies 140, as illustrated by the timing diagram in FIG. 2 for determining a status of a flash memory device “physical unit”.
performing a read operation on the first physical unit and determining whether a data error condition is met;
At time t.sub.a 252, a first check status command 220 may be sent to determine the status of the flash memory die. At time t.sub.c 256, a second check status command 230 may be sent after the time interval 244 has elapsed. However, in instances where the first and second ready status signals differ or do not match, the controller 120 may flag the flash memory die as failed “data error condition is met".
A false positive can be therefore detected by comparing the two sets of status bits, respectively, from the first ready status signal 225 and the second ready status signal 235.
marking the first physical unit as “bad” when the data error condition is met and an elapsed time indicated by the timer is less than a threshold time. FIG. 2 is discussed further in reference to FIG. 3. [0042] Alternatively, at 316 the controller 120 may determine that the first signal unsuccessfully matches the second signal by determining that the first plurality of bits is different than the second plurality of bits (e.g., the respective plurality of bits do not match with each other). At 318, the controller 120 provides, in response to determining that the first signal unsuccessfully matches the second signal, an indication of a failure of the flash memory device corresponding to “bad physical unit when the data error condition is met”.
Regarding independent Claims 8 and 15, CHU additionally discloses a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units; and a, coupled to the connection interface unit and the rewritable non-volatile memory module, [0016] As depicted in FIG. 1, the flash storage system 110 “rewritable non-volatile memory module” includes an interface 115, a controller 120 “memory control circuit unit”, a memory 125, a decoder 160, an encoder 166, and flash memory devices 130 “physical units”. The interface 115 facilitates communication of data, commands, and/or control signals between the flash storage system 110 and a host 150. The controller 120 controls the operation of the flash storage system 110 to store and retrieve data in the flash memory devices 130 (e.g., illustrated as flash memory device 130(a), 130(b) to 130(n) to depict at least several devices) in accordance with commands received from the host 150 and an internal management processor 145.
Regarding Claims 2, 3, 6, 9, 13, 16, 17, 20, CHU discloses “resetting the timer” [0044] The process of FIG. 4 starts after an indication of a failure of the flash memory device is detected. At 402, the flash storage system 110 sends, in response to the indication of the failure of the flash memory device, a reset command for the flash memory device. At 404, the flash storage system 110 sends an initialization command for the flash memory device which may attempt to reset the flash memory device back to factory settings or some predetermined state.
Regarding Claims 4, 10, 11, 18, CHU discloses wherein the read operation comprises a hard decoding process, configured to detect a plurality of error bits in the first physical unit, [0027] In FIG. 1, In an example, a read operation starts with a request for data, for example from the host 150 or the controller 120. The controller 120 sends a read command to the appropriate flash memory device 130 storing the requested data. The flash memory device 130 provides data, for example in a buffer, which the decoder 160 decodes for a hard decode operation. More specifically, the hard decoder 162 may decode the data for the hard decode operation “hard decoding process”. The decoder 160 returns an indication to the controller 120 after completing the hard decode operation. If the indication indicates successful decoding, the controller 120 returns the decoded data to the host 150 in response to the request for data.
Regarding Claims 5, 12, 19, CHU discloses performing a soft decoding process and adding the number of errors when the hard decoding process fails;
[0026] The hard decoders 162 may be decoders that are reserved for hard decoding. Hard decoding limits the read bit values to either a “1” or a “0.” Soft decoding, on the other hand, uses a range of values pulled from an LLR table, for example, to provide reliability or confidence measures that the read values are correct. The LLR table allows the confidence values to be looked up based on the read outcomes. The soft decoders 164 may be decoders that are reserved for soft decoding. In certain implementations, the number of hard decoders 162 and the number of soft decoder 164 may be dynamically reserved from a pool of available decoders.
Regarding Claims 7, 14, 21, CHU discloses performing a cross-frame decoding when the soft decoding process fails and the data error condition is met is based on non-RAID ECC parity information, [0029] Different techniques may be used to detect die failure on the flash memory devices 130. In an example, the controller 120 could check for a transition of a DQS signal in a read direction within a time window. As mentioned before, using the DQS signal in this manner may have a disadvantage of an inaccurate detection of die failure. To detect a failure of a flash memory die and mitigate an inaccurate detection of die failure, the subject technology provides implementations using two check status commands that are sent in a successive manner.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
US 20180211713 Zeng; Shih-Jia et al. [0023] In the decoding process C, a soft decoding operation is performed according to the retry read voltage set. Generally, the soft decoding operation has better error correction capability than the hard decoding operation. However, in comparison with the read voltage set for the hard decoding operation, the read voltage set for the soft decoding operation contains more read voltages. In contrast, the read voltage set for the soft decoding operation contains nine read voltages. Consequently, the time period of performing the decoding process C is longer than the time period of performing the decoding process B.
US 20170322842 IWAKI; HIROYUKI et al. [0098] If the host computer 100 supplies the read command designating the address A to the memory controller 300 within a fixed period of time after the writing of data, the memory controller 300 returns the read error without performing read access.
US 20220004339 Lin; Ching-Hui [0040] After a period of time, the charges stored in gates of some memory cells do not represent the charges of original data any more, such that errors often occur when the memory cells are read. These errors usually cause the flash memory controller to start some correction mechanisms such as changing the read voltage and hard decoding and soft decoding, such that correct data can be read from the expired blocks. These correction mechanisms are usually very time-consuming and power-consuming, and may not be able to correct the error at all, which makes the flash memory controller fail to read the correct data.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: July 1, 2026
Non-Final Rejection 20260701
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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