DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,253,563. Although the claims at issue are not identical, they are not patentably distinct from each other because they recite essentially the same limitations.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 14-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claim 14, Line 2 “the current source” has no antecedent basis. The Examiner is interpreting “a source current,” also in Line 2, as “a current source.”
Regarding Claim 15, “the calibration mode” has no antecedent basis.
Claims 16-20 are rejected as depending on Claim 14.
Claim Objections
Claim 18 is objected to because of the following informalities: “a second clock signal” already has antecedent basis in Claim 17. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 14, 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal (US 2008/0218151 A1, Pub Sep 11, 2008) in view of Berkhout (US 2014/0312963 A1, Pub Oct 23, 2014).
Regarding Claim 1, Agarwal teaches:
A duty cycle measurement (DCM) device (circuit 100 for measuring the duty cycle of an unknown clock signal [0051] Fig 1-4) comprising:
a charge pump circuit (Source VDD, Capacitor 102, Switch 106 and current source 110 all make up the "charge pump circuit" [0051]) configured to generate a capacitor voltage (VCOMP [0054]) based on a duty cycle (duty cycle [0052]) of a clock signal (CLK [0052]), wherein
the charge pump circuit comprises at least one current source (110)
a clocked comparator circuit (counter 104 and comparator circuit 108 make up the "clocked comparator circuit" [0051]) configured to generate a digital output code (Counter 104 outputs a digital output code of N Bits representing the elapsed cycle based on the output of comparator 108, which is thereby based on the comparison between VCOMP and VREF [0054]) based on the capacitor voltage (VCOMP).
Agarwal does not teach:
at least one current source having a first terminal connected to a capacitor voltage node having the capacitor voltage;
However, Berkhout teaches:
The Examiner is combining Agarwal in view of Berkhout by substituting the switch 106 and current source 110 of Agarwal with the current switch shown in Figure 2 of Berkhout, and connecting signal CLK of Agarwal to terminal ctrl of Berkhout and connecting the drain terminal of Mout of Berkhout to the VCOMP node of Agarwal. The source terminal of Mout of Berkhout would be connected to the ground of Agarwal.
at least one current source (Figure 2 of Berkhout shows a current switch, which is a current source has a third terminal to control whether the current source is on or off) having a first terminal connected to a capacitor voltage node having the capacitor voltage (As explained above the drain terminal - "first terminal" - of Mout would be connected to node VCOMP of Agarwal);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Agarwal in view of Berkhout by having at least one current source having a first terminal connected to a capacitor voltage node having the capacitor voltage because it is a simple substitution of a series switch and current source for a current switch that obtains the predictable result of being able to control whether a current source provides current or not as taught by Berkhout [0010].
Regarding Claim 14, Agarwal teaches:
A method of determining a duty cycle of a clock signal (A method for measuring a duty cycle of an unknown clock signal [0059]. Fig 1-4), the method comprising:
generating a first capacitor voltage based on a duty cycle of the first clock signal (Based on the "duty cycle" of the clock signal CLK - "first clock signal" - with a reference duty cycle applied to switch 106 in step 206, the capacitor voltage VCOMP - "first capacitor voltage" - changes [0052].; see Fig 1-4); and
generating a first digital output code based on the first capacitor voltage (In Step 208, number of clock cycles N1 - "first digital output code" - is representative of a number of clock cycles based on the reference duty cycle is generated based on the "first capacitor voltage" VCOMP [0052].; see Fug 1-4).
Agarwal does not teach:
receiving, by a source current, a first clock signal, wherein the current source has a first terminal connected to a capacitor voltage node;
However, Berkhout teaches:
The Examiner is combining Agarwal in view of Berkhout by substituting the switch 106 and current source 110 of Agarwal with the current switch shown in Figure 2 of Berkhout, and connecting signal CLK of Agarwal to terminal ctrl of Berkhout and connecting the drain terminal of Mout of Berkhout to the VCOMP node of Agarwal. The source terminal of Mout of Berkhout would be connected to the ground of Agarwal.
receiving, by a source current (Figure 2 of Berkhout shows a current switch, which is a current source has a third terminal to control whether the current source is on or off), a first clock signal (signal CLK of Agarwal as explained above), wherein the current source (Figure 2 of Berkhout) has a first terminal connected to a capacitor voltage node (As explained above the drain terminal of Mout would be connected to node VCOMP of Agarwal);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Agarwal in view of Berkhout by having receiving, by a source current, a first clock signal, wherein the current source has a first terminal connected to a capacitor voltage node because it is a simple substitution of a series switch and current source for a current switch that obtains the predictable result of being able to control whether a current source provides current or not as taught by Berkhout [0010].
Regarding Claim 16, Agarwal teaches:
generating the first capacitor voltage (VCOMP) includes charging (Step 204) and discharging (Step 206) a capacitor (102) based on the duty cycle (The duty cycle of the clock determines N1) of the first clock signal (CLK signal applied to switch 106 in Step 206).
Regarding Claim 17, Agarwal teaches:
operating in a measurement mode (Steps 210-212 are operating in a measurement mode [0060]);
receiving a second clock signal that has an unknown duty cycle (In Step 212, a clock signal with an unknown duty cycle is applied to switch 106);
generating a second capacitor voltage based on the duty cycle of the second clock signal (In Step 212, voltage VCOMP - "second capacitor voltage" - is generated based on the duty cycle of the clock signal with the unknown duty cycle);
comparing the second capacitor voltage with a reference voltage (Comparator 108 compares VCOMP with VREF - "reference voltage" [0052]);
generating the second digital output code based on the result of the comparison; and receiving the second digital output code (In Step 214, number of clock cycles N2 - "second digital output code" - is representative of a number of clock cycles based on the unknown duty cycle is generated based on the "second capacitor voltage" VCOMP [0052]. N2 is output.; see Fig 1-4).
Regarding Claim 19, Agarwal teaches:
generating the second capacitor voltage (VCOMP as generated in Step 212) includes charging (Step 210) and discharging (Step 212) a capacitor (102) based on the duty cycle of the second clock signal (the duty cycle of the clock signal of an unknown duty cycle).
Regarding Claim 20, Agarwal teaches:
providing the first digital output (N1) code as an output; and providing the second digital output code (N2) as an output (N1 and N2 have to be output so that in Step 216, they can be used to calculate the duty cycle of the clock signal with the unknown duty cycle as per the equation provided in [0058]).
Claims 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal in view of Berkhout and further in view of Boerstler et al. (US 2009/0112555 A1, Pub April 30, 2009, herein Boerstler).
Regarding Claim 6, Agarwal teaches:
A duty cycle measurement (DCM) device (circuit 100 for measuring the duty cycle of an unknown clock signal [0051] Fig 1-4) comprising:
a clock select circuit configured to provide a first clock signal;
a charge pump circuit (Source VDD, Capacitor 102, Switch 106 and current source 110 all make up the "charge pump circuit" [0051]) configured to generate a capacitor voltage (VCOMP [0054]) based on a duty cycle (duty cycle [0052]) of a clock signal (CLK [0052]), wherein
the charge pump circuit comprises at least one current source (110)
a clocked comparator circuit (counter 104 and comparator circuit 108 make up the "clocked comparator circuit" [0051]) configured to generate a digital output code (Counter 104 outputs a digital output code of N Bits representing the elapsed cycle based on the output of comparator 108, which is thereby based on the comparison between VCOMP and VREF [0054]) based on the capacitor voltage (VCOMP).
Agarwal does not teach:
at least one current source having a first terminal connected to a capacitor voltage node having the capacitor voltage;
However, Berkhout teaches:
The Examiner is combining Agarwal in view of Berkhout by substituting the switch 106 and current source 110 of Agarwal with the current switch shown in Figure 2 of Berkhout, and connecting signal CLK of Agarwal to terminal ctrl of Berkhout and connecting the drain terminal of Mout of Berkhout to the VCOMP node of Agarwal. The source terminal of Mout of Berkhout would be connected to the ground of Agarwal.
at least one current source (Figure 2 of Berkhout shows a current switch, which is a current source has a third terminal to control whether the current source is on or off) having a first terminal connected to a capacitor voltage node having the capacitor voltage (As explained above the drain terminal - "first terminal" - of Mout would be connected to node VCOMP of Agarwal);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Agarwal in view of Berkhout by having at least one current source having a first terminal connected to a capacitor voltage node having the capacitor voltage because it is a simple substitution of a series switch and current source for a current switch that obtains the predictable result of being able to control whether a current source provides current or not as taught by Berkhout [0010].
Agarwal and Berkhout do not teach:
a clock select circuit configured to provide a first clock signal;
However, Boerstler teaches:
The Examiner is combining Agarwal and Berkhout in view of Boerstler by using the output of MUX 142 of Boerstler as the CLK signal in Figure 1 of Agarwal.
a clock select circuit configured to provide a first clock signal ("Clock select circuit" 104 provides external clock signal CLK_CALIB - "first clock signal".; see Fig 1 & [0021-0023]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Chien in view of Boerstler by having a clock select circuit configured to provide a first clock signal because a calibration mode verifies proper operation of the duty cycle measurement circuit as taught by Boerstler [0021].
Regarding Claim 11, Agarwal and Berkhout do not teach the limitations.
However, Boerstler teaches:
the clock select circuit is further configured to receive a second clock signal that has an unknown duty cycle and a clock select signal and to provide at the output thereof one of the first and second clock signals based on the clock select signal (Clock select circuit 104 receives CLK_TEST signal - "second clock signal that has an unknown duty cycle" and CLK_SEL - "clock select signal" - and provides CLK_IN - "output" - of either CLK_TEST or CLK_CALIB based on CLK_SEL.; see Fig 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Agarwal and Berkhout in view of Boerstler by having the clock select circuit is further configured to receive a second clock signal that has an unknown duty cycle and a clock select signal and to provide at the output thereof one of the first and second clock signals based on the clock select signal because by operating in the calibration mode before the test mode, the proper operation of the duty cycle measurement circuit can be verified and then there can be a high level of confidence in the operation of the duty cycle measurement circuit in the test mode as taught by Boerstler [0021-0022].
Claims 12-13, 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal in view of Berkhout and further in view of Boerstler and further in view of Fortier et al. (US 11,652,489 B1, Filing Date April 18, 2022, herein Fortier).
Regarding Claim 12, Agarwal, Berkhout and Boerstler do not teach the limitations.
However, Fortier teaches:
the clock select circuit includes a frequency divider configured to receive a second clock signal and to divide a frequency of the second clock signal to obtain the first clock signal (Frequency divider circuitry 150 - "frequency divider" - receives the signal - "second clock signal" - from VCO circuitry 140 and outputs a frequency divided signal - "first clock signal" - to multiplexer 152.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Agarwal, Berkhout and Boerstler in view of Fortier by having the clock select circuit includes a frequency divider configured to receive a second clock signal and to divide a frequency of the second clock signal to obtain the first clock signal because it allows for the output of a selected clock signal that has a duty cycle-adjusted signal of 50% as taught by Fortier [5:38-56], [8:25-57].
Regarding Claim 13, Agarwal and Berkhout do not teach the limitations.
However, Boerstler teaches:
the clock select circuit further includes a multiplexer configured to receive the first and second clock signals (Clock select circuit 104 has multiplexer 142 that receives CLK_CALIB - "first clock signal" - and CLK_TEST - "second clock signal".).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Agarwal, Berkhout and Fortier in view of Boerstler by having the clock select circuit includes a frequency divider configured to receive a second clock signal and to divide a frequency of the second clock signal to obtain the first clock signal because it allows for the output of a selected clock signal that has a duty cycle-adjusted signal of 50% as taught by Fortier [5:38-56], [8:25-57].
Regarding Claim 15, Agarwal and Berkhout do not teach the limitations.
However, Boerstler teaches:
operating in the calibration mode (When Mux 142 selects the CLK_CALIB signal [0032] Fig 1) includes:
receiving a second clock signal (CLK_TEST signal - "second clock signal" - is received at Mux 142);
receiving a clock select signal (CLK_SEL is received at MUX 142 [0032] Fig 1); and
providing the first clock signal as an output based on the clock select signal (MUX 142 outputs the CLK_CALIB signal - "first clock signal" - to become the CLK_IN signal - "output", when the CLK_SEL signal - "clock select signal" - selects the CLK_CALIB signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Agarwal and Berkhout in view of Boerstler by having operating in the calibration mode includes: receiving a second clock signal; receiving a clock select signal; and providing the first clock signal as an output based on the clock select signal because by operating in the calibration mode before the test mode, the proper operation of the duty cycle measurement circuit can be verified and then there can be a high level of confidence in the operation of the duty cycle measurement circuit in the test mode as taught by Boerstler [0021-0022].
Agarwal, Berkhout and Boerstler do not teach:
dividing a frequency of the second clock signal to obtain the first clock signal;
However, Fortier teaches:
dividing a frequency of the second clock signal to obtain the first clock signal (Frequency divider circuitry 150 - "dividing a frequency" - receives the signal - "second clock signal" - from VCO circuitry 140 and outputs a frequency divided signal - "first clock signal" - to multiplexer 152.);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Agarwal, Berkhout and Boerstler in view of Fortier by having dividing a frequency of the second clock signal to obtain the first clock signal because it allows for the output of a selected clock signal that has a duty cycle-adjusted signal of 50% as taught by Fortier [5:38-56], [8:25-57].
Regarding Claim 18, Agarwal and Berkhout do not teach the limitations.
However, Boerstler teaches:
operating in the measurement mode includes (When Mux 142 selects the CLK_TEST signal [0032] Fig 1):
receiving a second clock signal (CLK_TEST signal - "second clock signal" - is received at Mux 142);
receiving a clock select signal (CLK_SEL is received at MUX 142 [0032] Fig 1); and
providing the second clock signal as an output based on the clock select signal (MUX 142 outputs the CLK_TEST signal - "second clock signal" - to become the CLK_IN signal - "output", when the CLK_SEL signal - "clock select signal" - selects the CLK_CALIB signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Agarwal and Berkhout in view of Boerstler by having operating in the measurement mode includes: receiving a second clock signal; receiving a clock select signal; and providing the second clock signal as an output based on the clock select signal because by operating in the calibration mode before the test mode, the proper operation of the duty cycle measurement circuit can be verified and then there can be a high level of confidence in the operation of the duty cycle measurement circuit in the test mode as taught by Boerstler [0021-0022].
Allowable Subject Matter
Claims 2-5 and 7-10 have no prior art rejection applied to them, however, they do have a Double Patenting Rejection being applied to them.
Regarding Claim 2, the prior art of record fails to teach or suggest, singly or in combination:
“a first current source having a first current source terminal configured to receive a supply voltage, a second current source terminal connected to the capacitor voltage node, and a third current source terminal configured to receive the digital output code” in combination with the other limitations of the Claim.
Claims 3-5 depend on Claim 2.
Claim 7 has the same limitation as in Claim 2.
Claims 8-10 depend on Claim 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAHUL MAINI whose telephone number is (571)270-1099. The examiner can normally be reached M-Th, 9am-4pm, EST.
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/R.M/Examiner, Art Unit 2858 08/24/2026
/A.A/Primary Examiner, Art Unit 2858
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